Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	814870070	74984	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	814870070	74984	0	0
T1	1120870	1267	0	0
T2	0	821	0	0
T3	0	977	0	0
T4	83145	0	0	0
T7	4790	0	0	0
T10	0	69	0	0
T11	0	190	0	0
T12	0	74	0	0
T13	0	302	0	0
T14	0	211	0	0
T15	0	1131	0	0
T16	0	44	0	0
T17	12435	0	0	0
T18	12785	0	0	0
T19	10630	0	0	0
T20	4470	0	0	0
T21	6455	0	0	0
T22	9295	0	0	0
T23	12315	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162974014	11151	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	11151	0	0
T1	224174	167	0	0
T2	0	129	0	0
T3	0	156	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	13	0	0
T11	0	24	0	0
T12	0	10	0	0
T13	0	37	0	0
T14	0	27	0	0
T15	0	183	0	0
T16	0	7	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162974014	11006	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	11006	0	0
T1	224174	164	0	0
T2	0	128	0	0
T3	0	154	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	13	0	0
T11	0	24	0	0
T12	0	11	0	0
T13	0	43	0	0
T14	0	27	0	0
T15	0	181	0	0
T16	0	7	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162974014	15099	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	15099	0	0
T1	224174	257	0	0
T2	0	168	0	0
T3	0	198	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	13	0	0
T11	0	39	0	0
T12	0	14	0	0
T13	0	60	0	0
T14	0	43	0	0
T15	0	230	0	0
T16	0	9	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162974014	15036	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	15036	0	0
T1	224174	259	0	0
T2	0	167	0	0
T3	0	199	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	13	0	0
T11	0	38	0	0
T12	0	15	0	0
T13	0	60	0	0
T14	0	43	0	0
T15	0	229	0	0
T16	0	9	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162974014	22692	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	22692	0	0
T1	224174	420	0	0
T2	0	229	0	0
T3	0	270	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	17	0	0
T11	0	65	0	0
T12	0	24	0	0
T13	0	102	0	0
T14	0	71	0	0
T15	0	308	0	0
T16	0	12	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0