Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
6308336 |
6267891 |
0 |
0 |
T4 |
959738 |
957075 |
0 |
0 |
T6 |
120777 |
119150 |
0 |
0 |
T7 |
36569 |
32172 |
0 |
0 |
T17 |
65149 |
60114 |
0 |
0 |
T18 |
67063 |
64086 |
0 |
0 |
T19 |
289508 |
287680 |
0 |
0 |
T20 |
57750 |
55474 |
0 |
0 |
T21 |
34463 |
30436 |
0 |
0 |
T22 |
71954 |
69369 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
977844084 |
963544134 |
0 |
14490 |
T1 |
1345044 |
1335150 |
0 |
18 |
T4 |
99774 |
99462 |
0 |
18 |
T6 |
11544 |
11340 |
0 |
18 |
T7 |
5748 |
4968 |
0 |
18 |
T17 |
14922 |
13632 |
0 |
18 |
T18 |
15342 |
14574 |
0 |
18 |
T19 |
12756 |
12642 |
0 |
18 |
T20 |
5364 |
5106 |
0 |
18 |
T21 |
7746 |
6768 |
0 |
18 |
T22 |
11154 |
10680 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1556882 |
1545325 |
0 |
21 |
T4 |
334385 |
333284 |
0 |
21 |
T6 |
42039 |
41331 |
0 |
21 |
T7 |
11425 |
9889 |
0 |
21 |
T17 |
17310 |
15814 |
0 |
21 |
T18 |
17921 |
17025 |
0 |
21 |
T19 |
109770 |
108883 |
0 |
21 |
T20 |
20289 |
19350 |
0 |
21 |
T21 |
9322 |
8143 |
0 |
21 |
T22 |
22530 |
21589 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
206573 |
0 |
0 |
T1 |
1556882 |
1817 |
0 |
0 |
T2 |
0 |
156 |
0 |
0 |
T4 |
334385 |
4 |
0 |
0 |
T6 |
42039 |
177 |
0 |
0 |
T7 |
11425 |
16 |
0 |
0 |
T17 |
17310 |
269 |
0 |
0 |
T18 |
17921 |
124 |
0 |
0 |
T19 |
109770 |
211 |
0 |
0 |
T20 |
20289 |
16 |
0 |
0 |
T21 |
9322 |
12 |
0 |
0 |
T22 |
22530 |
16 |
0 |
0 |
T23 |
0 |
91 |
0 |
0 |
T70 |
0 |
164 |
0 |
0 |
T71 |
0 |
27 |
0 |
0 |
T112 |
0 |
7 |
0 |
0 |
T113 |
0 |
87 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3406410 |
3387402 |
0 |
0 |
T4 |
525579 |
524290 |
0 |
0 |
T6 |
67194 |
66440 |
0 |
0 |
T7 |
19396 |
17276 |
0 |
0 |
T17 |
32917 |
30629 |
0 |
0 |
T18 |
33800 |
32448 |
0 |
0 |
T19 |
166982 |
166116 |
0 |
0 |
T20 |
32097 |
30979 |
0 |
0 |
T21 |
17395 |
15486 |
0 |
0 |
T22 |
38270 |
37061 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
520093574 |
516384260 |
0 |
0 |
T1 |
207582 |
205985 |
0 |
0 |
T4 |
35055 |
34865 |
0 |
0 |
T6 |
7391 |
7270 |
0 |
0 |
T7 |
1841 |
1596 |
0 |
0 |
T17 |
2388 |
2185 |
0 |
0 |
T18 |
2479 |
2358 |
0 |
0 |
T19 |
20422 |
20260 |
0 |
0 |
T20 |
3581 |
3419 |
0 |
0 |
T21 |
1304 |
1142 |
0 |
0 |
T22 |
3640 |
3492 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
520093574 |
516377306 |
0 |
2415 |
T1 |
207582 |
205983 |
0 |
3 |
T4 |
35055 |
34862 |
0 |
3 |
T6 |
7391 |
7267 |
0 |
3 |
T7 |
1841 |
1593 |
0 |
3 |
T17 |
2388 |
2182 |
0 |
3 |
T18 |
2479 |
2355 |
0 |
3 |
T19 |
20422 |
20257 |
0 |
3 |
T20 |
3581 |
3416 |
0 |
3 |
T21 |
1304 |
1139 |
0 |
3 |
T22 |
3640 |
3489 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
520093574 |
29340 |
0 |
0 |
T1 |
207582 |
260 |
0 |
0 |
T4 |
35055 |
0 |
0 |
0 |
T6 |
7391 |
56 |
0 |
0 |
T7 |
1841 |
8 |
0 |
0 |
T17 |
2388 |
62 |
0 |
0 |
T18 |
2479 |
0 |
0 |
0 |
T19 |
20422 |
56 |
0 |
0 |
T20 |
3581 |
4 |
0 |
0 |
T21 |
1304 |
0 |
0 |
0 |
T22 |
3640 |
0 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T70 |
0 |
59 |
0 |
0 |
T112 |
0 |
4 |
0 |
0 |
T113 |
0 |
45 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T17 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T17 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T17 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T17 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
18548 |
0 |
0 |
T1 |
224174 |
137 |
0 |
0 |
T2 |
0 |
156 |
0 |
0 |
T4 |
16629 |
0 |
0 |
0 |
T6 |
1924 |
27 |
0 |
0 |
T7 |
958 |
0 |
0 |
0 |
T17 |
2487 |
71 |
0 |
0 |
T18 |
2557 |
0 |
0 |
0 |
T19 |
2126 |
33 |
0 |
0 |
T20 |
894 |
4 |
0 |
0 |
T21 |
1291 |
0 |
0 |
0 |
T22 |
1859 |
0 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T70 |
0 |
66 |
0 |
0 |
T71 |
0 |
27 |
0 |
0 |
T113 |
0 |
27 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
20956 |
0 |
0 |
T1 |
224174 |
208 |
0 |
0 |
T4 |
16629 |
0 |
0 |
0 |
T6 |
1924 |
20 |
0 |
0 |
T7 |
958 |
4 |
0 |
0 |
T17 |
2487 |
56 |
0 |
0 |
T18 |
2557 |
0 |
0 |
0 |
T19 |
2126 |
38 |
0 |
0 |
T20 |
894 |
2 |
0 |
0 |
T21 |
1291 |
0 |
0 |
0 |
T22 |
1859 |
0 |
0 |
0 |
T23 |
0 |
45 |
0 |
0 |
T70 |
0 |
39 |
0 |
0 |
T112 |
0 |
3 |
0 |
0 |
T113 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
550835404 |
0 |
0 |
T1 |
225238 |
224228 |
0 |
0 |
T4 |
66518 |
66434 |
0 |
0 |
T6 |
7700 |
7674 |
0 |
0 |
T7 |
1917 |
1777 |
0 |
0 |
T17 |
2487 |
2418 |
0 |
0 |
T18 |
2582 |
2542 |
0 |
0 |
T19 |
21274 |
21234 |
0 |
0 |
T20 |
3730 |
3647 |
0 |
0 |
T21 |
1359 |
1247 |
0 |
0 |
T22 |
3793 |
3738 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
550835404 |
0 |
0 |
T1 |
225238 |
224228 |
0 |
0 |
T4 |
66518 |
66434 |
0 |
0 |
T6 |
7700 |
7674 |
0 |
0 |
T7 |
1917 |
1777 |
0 |
0 |
T17 |
2487 |
2418 |
0 |
0 |
T18 |
2582 |
2542 |
0 |
0 |
T19 |
21274 |
21234 |
0 |
0 |
T20 |
3730 |
3647 |
0 |
0 |
T21 |
1359 |
1247 |
0 |
0 |
T22 |
3793 |
3738 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
520093574 |
518273359 |
0 |
0 |
T1 |
207582 |
206613 |
0 |
0 |
T4 |
35055 |
34975 |
0 |
0 |
T6 |
7391 |
7366 |
0 |
0 |
T7 |
1841 |
1706 |
0 |
0 |
T17 |
2388 |
2322 |
0 |
0 |
T18 |
2479 |
2440 |
0 |
0 |
T19 |
20422 |
20383 |
0 |
0 |
T20 |
3581 |
3501 |
0 |
0 |
T21 |
1304 |
1197 |
0 |
0 |
T22 |
3640 |
3588 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
520093574 |
518273359 |
0 |
0 |
T1 |
207582 |
206613 |
0 |
0 |
T4 |
35055 |
34975 |
0 |
0 |
T6 |
7391 |
7366 |
0 |
0 |
T7 |
1841 |
1706 |
0 |
0 |
T17 |
2388 |
2322 |
0 |
0 |
T18 |
2479 |
2440 |
0 |
0 |
T19 |
20422 |
20383 |
0 |
0 |
T20 |
3581 |
3501 |
0 |
0 |
T21 |
1304 |
1197 |
0 |
0 |
T22 |
3640 |
3588 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
261294892 |
261294892 |
0 |
0 |
T1 |
103391 |
103391 |
0 |
0 |
T4 |
17488 |
17488 |
0 |
0 |
T6 |
4042 |
4042 |
0 |
0 |
T7 |
868 |
868 |
0 |
0 |
T17 |
1320 |
1320 |
0 |
0 |
T18 |
1220 |
1220 |
0 |
0 |
T19 |
11482 |
11482 |
0 |
0 |
T20 |
1808 |
1808 |
0 |
0 |
T21 |
599 |
599 |
0 |
0 |
T22 |
1794 |
1794 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
261294892 |
261294892 |
0 |
0 |
T1 |
103391 |
103391 |
0 |
0 |
T4 |
17488 |
17488 |
0 |
0 |
T6 |
4042 |
4042 |
0 |
0 |
T7 |
868 |
868 |
0 |
0 |
T17 |
1320 |
1320 |
0 |
0 |
T18 |
1220 |
1220 |
0 |
0 |
T19 |
11482 |
11482 |
0 |
0 |
T20 |
1808 |
1808 |
0 |
0 |
T21 |
599 |
599 |
0 |
0 |
T22 |
1794 |
1794 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130646752 |
130646752 |
0 |
0 |
T1 |
516951 |
516951 |
0 |
0 |
T4 |
8744 |
8744 |
0 |
0 |
T6 |
2021 |
2021 |
0 |
0 |
T7 |
434 |
434 |
0 |
0 |
T17 |
658 |
658 |
0 |
0 |
T18 |
610 |
610 |
0 |
0 |
T19 |
5740 |
5740 |
0 |
0 |
T20 |
904 |
904 |
0 |
0 |
T21 |
299 |
299 |
0 |
0 |
T22 |
897 |
897 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130646752 |
130646752 |
0 |
0 |
T1 |
516951 |
516951 |
0 |
0 |
T4 |
8744 |
8744 |
0 |
0 |
T6 |
2021 |
2021 |
0 |
0 |
T7 |
434 |
434 |
0 |
0 |
T17 |
658 |
658 |
0 |
0 |
T18 |
610 |
610 |
0 |
0 |
T19 |
5740 |
5740 |
0 |
0 |
T20 |
904 |
904 |
0 |
0 |
T21 |
299 |
299 |
0 |
0 |
T22 |
897 |
897 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
265272145 |
264341983 |
0 |
0 |
T1 |
107252 |
106767 |
0 |
0 |
T4 |
31928 |
31889 |
0 |
0 |
T6 |
3696 |
3683 |
0 |
0 |
T7 |
920 |
853 |
0 |
0 |
T17 |
1194 |
1161 |
0 |
0 |
T18 |
1239 |
1220 |
0 |
0 |
T19 |
10212 |
10193 |
0 |
0 |
T20 |
1790 |
1751 |
0 |
0 |
T21 |
652 |
598 |
0 |
0 |
T22 |
1820 |
1794 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
265272145 |
264341983 |
0 |
0 |
T1 |
107252 |
106767 |
0 |
0 |
T4 |
31928 |
31889 |
0 |
0 |
T6 |
3696 |
3683 |
0 |
0 |
T7 |
920 |
853 |
0 |
0 |
T17 |
1194 |
1161 |
0 |
0 |
T18 |
1239 |
1220 |
0 |
0 |
T19 |
10212 |
10193 |
0 |
0 |
T20 |
1790 |
1751 |
0 |
0 |
T21 |
652 |
598 |
0 |
0 |
T22 |
1820 |
1794 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160590689 |
0 |
2415 |
T1 |
224174 |
222525 |
0 |
3 |
T4 |
16629 |
16577 |
0 |
3 |
T6 |
1924 |
1890 |
0 |
3 |
T7 |
958 |
828 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2557 |
2429 |
0 |
3 |
T19 |
2126 |
2107 |
0 |
3 |
T20 |
894 |
851 |
0 |
3 |
T21 |
1291 |
1128 |
0 |
3 |
T22 |
1859 |
1780 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162974014 |
160597757 |
0 |
0 |
T1 |
224174 |
222526 |
0 |
0 |
T4 |
16629 |
16580 |
0 |
0 |
T6 |
1924 |
1893 |
0 |
0 |
T7 |
958 |
831 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2557 |
2432 |
0 |
0 |
T19 |
2126 |
2110 |
0 |
0 |
T20 |
894 |
854 |
0 |
0 |
T21 |
1291 |
1131 |
0 |
0 |
T22 |
1859 |
1783 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548857145 |
0 |
2415 |
T1 |
225238 |
223573 |
0 |
3 |
T4 |
66518 |
66317 |
0 |
3 |
T6 |
7700 |
7571 |
0 |
3 |
T7 |
1917 |
1660 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2582 |
2453 |
0 |
3 |
T19 |
21274 |
21103 |
0 |
3 |
T20 |
3730 |
3558 |
0 |
3 |
T21 |
1359 |
1187 |
0 |
3 |
T22 |
3793 |
3635 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
34414 |
0 |
0 |
T1 |
225238 |
298 |
0 |
0 |
T4 |
66518 |
1 |
0 |
0 |
T6 |
7700 |
19 |
0 |
0 |
T7 |
1917 |
1 |
0 |
0 |
T17 |
2487 |
22 |
0 |
0 |
T18 |
2582 |
31 |
0 |
0 |
T19 |
21274 |
14 |
0 |
0 |
T20 |
3730 |
1 |
0 |
0 |
T21 |
1359 |
3 |
0 |
0 |
T22 |
3793 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548857145 |
0 |
2415 |
T1 |
225238 |
223573 |
0 |
3 |
T4 |
66518 |
66317 |
0 |
3 |
T6 |
7700 |
7571 |
0 |
3 |
T7 |
1917 |
1660 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2582 |
2453 |
0 |
3 |
T19 |
21274 |
21103 |
0 |
3 |
T20 |
3730 |
3558 |
0 |
3 |
T21 |
1359 |
1187 |
0 |
3 |
T22 |
3793 |
3635 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
34331 |
0 |
0 |
T1 |
225238 |
308 |
0 |
0 |
T4 |
66518 |
1 |
0 |
0 |
T6 |
7700 |
19 |
0 |
0 |
T7 |
1917 |
1 |
0 |
0 |
T17 |
2487 |
16 |
0 |
0 |
T18 |
2582 |
35 |
0 |
0 |
T19 |
21274 |
22 |
0 |
0 |
T20 |
3730 |
1 |
0 |
0 |
T21 |
1359 |
3 |
0 |
0 |
T22 |
3793 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548857145 |
0 |
2415 |
T1 |
225238 |
223573 |
0 |
3 |
T4 |
66518 |
66317 |
0 |
3 |
T6 |
7700 |
7571 |
0 |
3 |
T7 |
1917 |
1660 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2582 |
2453 |
0 |
3 |
T19 |
21274 |
21103 |
0 |
3 |
T20 |
3730 |
3558 |
0 |
3 |
T21 |
1359 |
1187 |
0 |
3 |
T22 |
3793 |
3635 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
34485 |
0 |
0 |
T1 |
225238 |
282 |
0 |
0 |
T4 |
66518 |
1 |
0 |
0 |
T6 |
7700 |
21 |
0 |
0 |
T7 |
1917 |
1 |
0 |
0 |
T17 |
2487 |
9 |
0 |
0 |
T18 |
2582 |
31 |
0 |
0 |
T19 |
21274 |
26 |
0 |
0 |
T20 |
3730 |
3 |
0 |
0 |
T21 |
1359 |
3 |
0 |
0 |
T22 |
3793 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548857145 |
0 |
2415 |
T1 |
225238 |
223573 |
0 |
3 |
T4 |
66518 |
66317 |
0 |
3 |
T6 |
7700 |
7571 |
0 |
3 |
T7 |
1917 |
1660 |
0 |
3 |
T17 |
2487 |
2272 |
0 |
3 |
T18 |
2582 |
2453 |
0 |
3 |
T19 |
21274 |
21103 |
0 |
3 |
T20 |
3730 |
3558 |
0 |
3 |
T21 |
1359 |
1187 |
0 |
3 |
T22 |
3793 |
3635 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
34499 |
0 |
0 |
T1 |
225238 |
324 |
0 |
0 |
T4 |
66518 |
1 |
0 |
0 |
T6 |
7700 |
15 |
0 |
0 |
T7 |
1917 |
1 |
0 |
0 |
T17 |
2487 |
33 |
0 |
0 |
T18 |
2582 |
27 |
0 |
0 |
T19 |
21274 |
22 |
0 |
0 |
T20 |
3730 |
1 |
0 |
0 |
T21 |
1359 |
3 |
0 |
0 |
T22 |
3793 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
552758290 |
548864153 |
0 |
0 |
T1 |
225238 |
223574 |
0 |
0 |
T4 |
66518 |
66320 |
0 |
0 |
T6 |
7700 |
7574 |
0 |
0 |
T7 |
1917 |
1663 |
0 |
0 |
T17 |
2487 |
2275 |
0 |
0 |
T18 |
2582 |
2456 |
0 |
0 |
T19 |
21274 |
21106 |
0 |
0 |
T20 |
3730 |
3561 |
0 |
0 |
T21 |
1359 |
1190 |
0 |
0 |
T22 |
3793 |
3638 |
0 |
0 |