Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	162974014	160453267	0	0
AllClkBypReqTrue_A	162974014	142172	0	0
IoClkBypReqFalse_A	162974014	160367574	0	2415
IoClkBypReqTrue_A	162974014	223229	0	0
LcClkBypAckFalse_A	162974014	160461685	0	0
LcClkBypAckTrue_A	162974014	133754	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	160453267	0	0
T1	224174	222369	0	0
T4	16629	16579	0	0
T6	1924	1892	0	0
T7	958	803	0	0
T17	2487	2060	0	0
T18	2557	2431	0	0
T19	2126	1873	0	0
T20	894	853	0	0
T21	1291	1130	0	0
T22	1859	1782	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	142172	0	0
T1	224174	1569	0	0
T2	0	857	0	0
T4	16629	0	0	0
T7	958	27	0	0
T17	2487	214	0	0
T18	2557	0	0	0
T19	2126	236	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	215	0	0
T70	0	162	0	0
T71	0	147	0	0
T72	0	37	0	0
T112	0	4	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	160367574	0	2415
T1	224174	222312	0	3
T4	16629	16577	0	3
T6	1924	1591	0	3
T7	958	828	0	3
T17	2487	1881	0	3
T18	2557	2429	0	3
T19	2126	1706	0	3
T20	894	821	0	3
T21	1291	1128	0	3
T22	1859	1780	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	223229	0	0
T1	224174	2129	0	0
T2	0	1586	0	0
T4	16629	0	0	0
T6	1924	299	0	0
T7	958	0	0	0
T17	2487	391	0	0
T18	2557	0	0	0
T19	2126	401	0	0
T20	894	30	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	0	86	0	0
T70	0	523	0	0
T71	0	226	0	0
T113	0	404	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	160461685	0	0
T1	224174	222384	0	0
T4	16629	16579	0	0
T6	1924	1723	0	0
T7	958	830	0	0
T17	2487	2136	0	0
T18	2557	2431	0	0
T19	2126	1887	0	0
T20	894	827	0	0
T21	1291	1130	0	0
T22	1859	1782	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	133754	0	0
T1	224174	1416	0	0
T2	0	989	0	0
T4	16629	0	0	0
T6	1924	169	0	0
T7	958	0	0	0
T17	2487	138	0	0
T18	2557	0	0	0
T19	2126	222	0	0
T20	894	26	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	0	78	0	0
T70	0	254	0	0
T71	0	182	0	0
T113	0	119	0	0