Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16552	0	0
TransStop_A	2147483647	8473	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16552	0	0
T1	900952	148	0	0
T2	0	138	0	0
T3	0	392	0	0
T4	266076	0	0	0
T7	7668	0	0	0
T17	9952	0	0	0
T18	10332	35	0	0
T19	85096	0	0	0
T20	14924	0	0	0
T21	5436	0	0	0
T22	15172	4	0	0
T23	10052	0	0	0
T43	0	4	0	0
T73	0	11	0	0
T78	0	17	0	0
T87	0	8	0	0
T114	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8473	0	0
T1	900952	65	0	0
T2	0	64	0	0
T3	0	221	0	0
T4	266076	0	0	0
T7	7668	0	0	0
T10	0	9	0	0
T17	9952	0	0	0
T18	10332	18	0	0
T19	85096	0	0	0
T20	14924	0	0	0
T21	5436	0	0	0
T22	15172	4	0	0
T23	10052	0	0	0
T43	0	4	0	0
T73	0	4	0	0
T78	0	13	0	0
T87	0	6	0	0
T114	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	552758729	4037	0	0
TransStop_A	552758729	2082	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	4037	0	0
T1	225238	39	0	0
T2	0	30	0	0
T3	0	99	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	7	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	2	0	0
T78	0	5	0	0
T87	0	3	0	0
T114	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	2082	0	0
T1	225238	19	0	0
T2	0	13	0	0
T3	0	56	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	5	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T78	0	4	0	0
T87	0	2	0	0
T114	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	552758729	4193	0	0
TransStop_A	552758729	2196	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	4193	0	0
T1	225238	34	0	0
T2	0	37	0	0
T3	0	98	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	9	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	5	0	0
T87	0	1	0	0
T114	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	2196	0	0
T1	225238	15	0	0
T2	0	14	0	0
T3	0	57	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	5	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T78	0	4	0	0
T87	0	1	0	0
T114	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	552758729	4134	0	0
TransStop_A	552758729	2089	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	4134	0	0
T1	225238	37	0	0
T2	0	36	0	0
T3	0	92	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	8	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	4	0	0
T87	0	1	0	0
T114	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	2089	0	0
T1	225238	17	0	0
T2	0	22	0	0
T3	0	52	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T10	0	9	0	0
T17	2488	0	0	0
T18	2583	3	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T78	0	3	0	0
T87	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	552758729	4188	0	0
TransStop_A	552758729	2106	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	4188	0	0
T1	225238	38	0	0
T2	0	35	0	0
T3	0	103	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	11	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	3	0	0
T87	0	3	0	0
T114	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758729	2106	0	0
T1	225238	14	0	0
T2	0	15	0	0
T3	0	56	0	0
T4	66519	0	0	0
T7	1917	0	0	0
T17	2488	0	0	0
T18	2583	5	0	0
T19	21274	0	0	0
T20	3731	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T78	0	2	0	0
T87	0	2	0	0
T114	0	1	0	0