Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T59,T60
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T59,T60
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T59,T60
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T59,T60

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 10100 10100 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10100 10100 0 0
T1 10 10 0 0
T4 10 10 0 0
T6 10 10 0 0
T7 10 10 0 0
T17 10 10 0 0
T18 10 10 0 0
T19 10 10 0 0
T20 10 10 0 0
T21 10 10 0 0
T22 10 10 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2320828 2308940 0 0
T4 319466 318336 0 0
T6 49700 48940 0 0
T7 11960 10552 0 0
T17 16094 14854 0 0
T18 16260 15522 0 0
T19 138260 137252 0 0
T20 23626 22678 0 0
T21 8426 7518 0 0
T22 23888 22990 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T61,T62
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T61,T62
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T61,T63
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T61,T63

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 522856474 518974638 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522856474 518974638 0 0
T1 207582 205985 0 0
T4 35055 34865 0 0
T6 7391 7270 0 0
T7 1841 1596 0 0
T17 2388 2185 0 0
T18 2479 2358 0 0
T19 20422 20260 0 0
T20 3581 3419 0 0
T21 1304 1142 0 0
T22 3640 3492 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T61,T62
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T61,T62
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T59,T60
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T59,T60

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 522856474 518974638 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522856474 518974638 0 0
T1 207582 205985 0 0
T4 35055 34865 0 0
T6 7391 7270 0 0
T7 1841 1596 0 0
T17 2388 2185 0 0
T18 2479 2358 0 0
T19 20422 20260 0 0
T20 3581 3419 0 0
T21 1304 1142 0 0
T22 3640 3492 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T60,T61
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T60,T61
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT61,T63,T64
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT61,T63,T64

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 262633848 261645036 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262633848 261645036 0 0
T1 103391 103077 0 0
T4 17488 17433 0 0
T6 4042 3994 0 0
T7 868 813 0 0
T17 1320 1251 0 0
T18 1220 1179 0 0
T19 11482 11420 0 0
T20 1808 1767 0 0
T21 599 571 0 0
T22 1794 1746 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT60,T61,T63
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT60,T61,T63
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT59,T60,T61
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT59,T60,T61

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 262633848 261645036 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262633848 261645036 0 0
T1 103391 103077 0 0
T4 17488 17433 0 0
T6 4042 3994 0 0
T7 868 813 0 0
T17 1320 1251 0 0
T18 1220 1179 0 0
T19 11482 11420 0 0
T20 1808 1767 0 0
T21 599 571 0 0
T22 1794 1746 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T61,T63
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T61,T63
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T60,T61
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T60,T61

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 131316221 130821902 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131316221 130821902 0 0
T1 516951 515381 0 0
T4 8744 8716 0 0
T6 2021 1997 0 0
T7 434 406 0 0
T17 658 624 0 0
T18 610 589 0 0
T19 5740 5709 0 0
T20 904 883 0 0
T21 299 285 0 0
T22 897 873 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T59,T60
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T59,T60
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T60,T61
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T60,T61

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 131316221 130821902 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131316221 130821902 0 0
T1 516951 515381 0 0
T4 8744 8716 0 0
T6 2021 1997 0 0
T7 434 406 0 0
T17 658 624 0 0
T18 610 589 0 0
T19 5740 5709 0 0
T20 904 883 0 0
T21 299 285 0 0
T22 897 873 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT61,T63,T64
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT59,T61,T63
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT61,T63,T64
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T59,T61
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T59,T61

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT59,T61,T63

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 555636433 551562595 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555636433 551562595 0 0
T1 225238 223574 0 0
T4 66518 66320 0 0
T6 7700 7574 0 0
T7 1917 1663 0 0
T17 2487 2275 0 0
T18 2582 2456 0 0
T19 21274 21106 0 0
T20 3730 3561 0 0
T21 1359 1190 0 0
T22 3793 3638 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT61,T63,T64
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT61,T63,T64
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT58,T59,T61
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT58,T59,T61

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 555636433 551562595 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555636433 551562595 0 0
T1 225238 223574 0 0
T4 66518 66320 0 0
T6 7700 7574 0 0
T7 1917 1663 0 0
T17 2487 2275 0 0
T18 2582 2456 0 0
T19 21274 21106 0 0
T20 3730 3561 0 0
T21 1359 1190 0 0
T22 3793 3638 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T59,T64
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T59,T64
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT60,T65,T62
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT60,T65,T62

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 266653624 264683750 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266653624 264683750 0 0
T1 107252 106453 0 0
T4 31928 31834 0 0
T6 3696 3635 0 0
T7 920 798 0 0
T17 1194 1092 0 0
T18 1239 1179 0 0
T19 10212 10131 0 0
T20 1790 1709 0 0
T21 652 571 0 0
T22 1820 1746 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT58,T59,T62
11CoveredT1,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT58,T59,T60
10CoveredT1,T2,T3

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101CoveredT1,T4,T5
110CoveredT58,T59,T62
111CoveredT1,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT6,T1,T7
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011CoveredT1,T4,T5
1101CoveredT60,T65,T62
1110Not Covered
1111CoveredT1,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T4,T5
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T1,T7

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT60,T65,T62

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT6,T1,T7
1CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T7
0 Covered T1,T4,T5


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T1,T7
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T1,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 266653624 264683750 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266653624 264683750 0 0
T1 107252 106453 0 0
T4 31928 31834 0 0
T6 3696 3635 0 0
T7 920 798 0 0
T17 1194 1092 0 0
T18 1239 1179 0 0
T19 10212 10131 0 0
T20 1790 1709 0 0
T21 652 571 0 0
T22 1820 1746 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%