Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	162974014	17535198	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	17535198	0	57
T1	224174	635209	0	0
T2	0	56067	0	0
T3	0	898078	0	0
T4	16629	0	0	0
T7	958	0	0	0
T10	0	4146	0	0
T11	0	24363	0	0
T12	0	9655	0	1
T13	0	37899	0	0
T14	0	24790	0	1
T16	0	0	0	1
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0
T24	0	927	0	1
T25	0	0	0	1
T33	0	1058	0	1
T115	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1