Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	932240	0	0
SrcPulseCheck_M	2147483647	930638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	932240
T1	1484118	2822
T2	0	5026
T3	0	4787
T4	179410	178
T5	0	726
T7	7754	0
T10	0	2430
T11	0	212
T17	11980	0
T18	11888	0
T19	84008	0
T20	14533	0
T21	6050	0
T22	15571	0
T23	11818	0
T24	0	72
T28	0	814
T29	0	173
T30	0	70
T31	0	120
T59	17535	0
T61	10638	1
T63	8220	1
T64	19154	1
T119	11768	1
T120	20274	2
T121	24324	1
T122	6262	1
T123	17154	3
T124	5766	1
T125	6593	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	930638
T1	768019	2822
T2	0	4859
T3	0	4490
T4	51174	178
T5	0	726
T7	3320	0
T10	0	2430
T11	0	212
T17	6990	0
T18	7054	0
T19	21690	0
T20	4640	0
T21	3561	0
T22	6572	0
T23	6892	0
T24	0	72
T28	0	814
T29	0	173
T30	0	70
T31	0	120
T59	7529	0
T61	19458	1
T63	48274	1
T64	8034	1
T119	5654	1
T120	39074	2
T121	10318	1
T122	14722	1
T123	32170	3
T124	10219	1
T125	5955	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	522856474	24908	0	0
SrcPulseCheck_M	163881445	24908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	522856474	24908
T1	207582	169
T2	0	311
T3	0	269
T4	35055	10
T5	0	26
T7	1841	0
T10	0	98
T17	2388	0
T18	2479	0
T19	20422	0
T20	3581	0
T21	1304	0
T22	3640	0
T23	2412	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	24908
T1	224174	169
T2	0	311
T3	0	269
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	522856474	30695	0	0
SrcPulseCheck_M	163881445	30707	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	522856474	30695
T1	207582	173
T2	0	322
T3	0	280
T4	35055	10
T5	0	26
T7	1841	0
T10	0	98
T17	2388	0
T18	2479	0
T19	20422	0
T20	3581	0
T21	1304	0
T22	3640	0
T23	2412	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	30707
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	30685	0	0
SrcPulseCheck_M	522856474	30697	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	30685
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	522856474	30697
T1	207582	173
T2	0	322
T3	0	280
T4	35055	10
T5	0	26
T7	1841	0
T10	0	98
T17	2388	0
T18	2479	0
T19	20422	0
T20	3581	0
T21	1304	0
T22	3640	0
T23	2412	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	262633848	24908	0	0
SrcPulseCheck_M	163881445	24908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	262633848	24908
T1	103391	169
T2	0	311
T3	0	269
T4	17488	10
T5	0	26
T7	868	0
T10	0	98
T17	1320	0
T18	1220	0
T19	11482	0
T20	1808	0
T21	599	0
T22	1794	0
T23	1266	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	24908
T1	224174	169
T2	0	311
T3	0	269
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	262633848	30701	0	0
SrcPulseCheck_M	163881445	30718	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	262633848	30701
T1	103391	173
T2	0	322
T3	0	280
T4	17488	10
T5	0	26
T7	868	0
T10	0	98
T17	1320	0
T18	1220	0
T19	11482	0
T20	1808	0
T21	599	0
T22	1794	0
T23	1266	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	30718
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	30696	0	0
SrcPulseCheck_M	262633848	30705	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	30696
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262633848	30705
T1	103391	173
T2	0	322
T3	0	280
T4	17488	10
T5	0	26
T7	868	0
T10	0	98
T17	1320	0
T18	1220	0
T19	11482	0
T20	1808	0
T21	599	0
T22	1794	0
T23	1266	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	131316221	24908	0	0
SrcPulseCheck_M	163881445	24908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	131316221	24908
T1	516951	169
T2	0	311
T3	0	269
T4	8744	10
T5	0	26
T7	434	0
T10	0	98
T17	658	0
T18	610	0
T19	5740	0
T20	904	0
T21	299	0
T22	897	0
T23	632	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	24908
T1	224174	169
T2	0	311
T3	0	269
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	131316221	30602	0	0
SrcPulseCheck_M	163881445	30638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	131316221	30602
T1	516951	173
T2	0	322
T3	0	280
T4	8744	10
T5	0	26
T7	434	0
T10	0	98
T17	658	0
T18	610	0
T19	5740	0
T20	904	0
T21	299	0
T22	897	0
T23	632	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	30638
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	30599	0	0
SrcPulseCheck_M	131316221	30604	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	30599
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	131316221	30604
T1	516951	173
T2	0	322
T3	0	280
T4	8744	10
T5	0	26
T7	434	0
T10	0	98
T17	658	0
T18	610	0
T19	5740	0
T20	904	0
T21	299	0
T22	897	0
T23	632	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	555636433	24908	0	0
SrcPulseCheck_M	163881445	24908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	555636433	24908
T1	225238	169
T2	0	311
T3	0	269
T4	66518	10
T5	0	26
T7	1917	0
T10	0	98
T17	2487	0
T18	2582	0
T19	21274	0
T20	3730	0
T21	1359	0
T22	3793	0
T23	2513	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	24908
T1	224174	169
T2	0	311
T3	0	269
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	555636433	30641	0	0
SrcPulseCheck_M	163881445	30659	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	555636433	30641
T1	225238	173
T2	0	322
T3	0	280
T4	66518	10
T5	0	26
T7	1917	0
T10	0	98
T17	2487	0
T18	2582	0
T19	21274	0
T20	3730	0
T21	1359	0
T22	3793	0
T23	2513	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	30659
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	30637	0	0
SrcPulseCheck_M	555636433	30647	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	30637
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	555636433	30647
T1	225238	173
T2	0	322
T3	0	280
T4	66518	10
T5	0	26
T7	1917	0
T10	0	98
T17	2487	0
T18	2582	0
T19	21274	0
T20	3730	0
T21	1359	0
T22	3793	0
T23	2513	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	266653624	24553	0	0
SrcPulseCheck_M	163881445	24908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	266653624	24553
T1	107252	169
T2	0	311
T3	0	269
T4	31928	10
T5	0	26
T7	920	0
T10	0	98
T17	1194	0
T18	1239	0
T19	10212	0
T20	1790	0
T21	652	0
T22	1820	0
T23	1206	0
T28	0	34
T29	0	8
T30	0	7
T31	0	12

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	24908
T1	224174	169
T2	0	311
T3	0	269
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	14
T31	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	266653624	30502	0	0
SrcPulseCheck_M	163881445	30665	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	266653624	30502
T1	107252	173
T2	0	322
T3	0	280
T4	31928	10
T5	0	26
T7	920	0
T10	0	98
T17	1194	0
T18	1239	0
T19	10212	0
T20	1790	0
T21	652	0
T22	1820	0
T23	1206	0
T28	0	34
T29	0	8
T30	0	28
T31	0	47

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163881445	30665
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	28
T31	0	48

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	30399	0	0
SrcPulseCheck_M	266653624	30534	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	30399
T1	224174	173
T2	0	322
T3	0	280
T4	16629	10
T5	0	26
T7	958	0
T10	0	98
T17	2487	0
T18	2557	0
T19	2126	0
T20	894	0
T21	1291	0
T22	1859	0
T23	2463	0
T28	0	34
T29	0	8
T30	0	21
T31	0	47

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	266653624	30534
T1	107252	173
T2	0	322
T3	0	280
T4	31928	10
T5	0	26
T7	920	0
T10	0	98
T17	1194	0
T18	1239	0
T19	10212	0
T20	1790	0
T21	652	0
T22	1820	0
T23	1206	0
T28	0	34
T29	0	8
T30	0	28
T31	0	47

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T61,T63
1	0	Covered	T58,T61,T63
1	1	Covered	T58,T61,T126

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T61,T63
1	0	Covered	T58,T61,T126
1	1	Covered	T58,T61,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	37	0	0
SrcPulseCheck_M	522856474	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	37
T58	12228	3
T61	5319	2
T62	5794	1
T63	4110	2
T64	9577	1
T119	5884	1
T120	10137	1
T121	12162	1
T123	8577	1
T127	6417	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	522856474	37
T58	23478	3
T61	21278	2
T62	55629	1
T63	49326	2
T64	9676	1
T119	7060	1
T120	40547	1
T121	12162	1
T123	34307	1
T127	12572	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T58,T61,T126

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T61,T126
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	36	0	0
SrcPulseCheck_M	522856474	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	36
T58	12228	3
T59	17535	1
T60	13684	1
T61	5319	2
T62	5794	1
T64	9577	2
T119	5884	1
T121	12162	2
T123	8577	1
T128	12848	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	522856474	36
T58	23478	3
T59	16833	1
T60	25262	1
T61	21278	2
T62	55629	1
T64	9676	2
T119	7060	1
T121	12162	2
T123	34307	1
T128	12333	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T61,T63,T64
1	0	Covered	T61,T63,T64
1	1	Covered	T123,T129

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T61,T63,T64
1	0	Covered	T123,T129
1	1	Covered	T61,T63,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	25	0	0
SrcPulseCheck_M	262633848	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	25
T61	5319	1
T63	4110	1
T64	9577	1
T119	5884	1
T120	10137	2
T121	12162	1
T122	3131	1
T123	8577	3
T124	5766	1
T125	6593	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262633848	25
T61	9729	1
T63	24137	1
T64	4017	1
T119	2827	1
T120	19537	2
T121	5159	1
T122	7361	1
T123	16085	3
T124	10219	1
T125	5955	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T59,T60,T61
1	0	Covered	T59,T60,T61
1	1	Covered	T130,T131,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T59,T60,T61
1	0	Covered	T130,T131,T132
1	1	Covered	T59,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	32	0	0
SrcPulseCheck_M	262633848	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	32
T59	17535	1
T60	13684	1
T61	5319	1
T63	4110	2
T64	9577	1
T119	5884	1
T120	10137	2
T121	12162	1
T122	3131	1
T123	8577	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	262633848	32
T59	7529	1
T60	11822	1
T61	9729	1
T63	24137	2
T64	4017	1
T119	2827	1
T120	19537	2
T121	5159	1
T122	7361	1
T123	16085	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T60,T61
1	1	Covered	T122,T133,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T60,T61
1	0	Covered	T122,T133,T134
1	1	Covered	T58,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	38	0	0
SrcPulseCheck_M	131316221	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	38
T58	12228	1
T60	13684	2
T61	5319	1
T63	4110	2
T121	12162	2
T122	3131	3
T123	8577	2
T124	5766	1
T125	6593	1
T128	12848	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	131316221	38
T58	5505	1
T60	5913	2
T61	4861	1
T63	12071	2
T121	2581	2
T122	3680	3
T123	8045	2
T124	5106	1
T125	2978	1
T128	2590	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T60,T61
1	1	Covered	T58,T122,T135

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T122,T135
1	1	Covered	T58,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	36	0	0
SrcPulseCheck_M	131316221	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	36
T58	12228	2
T60	13684	2
T61	5319	1
T63	4110	2
T64	9577	1
T119	5884	1
T121	12162	2
T122	3131	2
T123	8577	2
T128	12848	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	131316221	36
T58	5505	2
T60	5913	2
T61	4861	1
T63	12071	2
T64	2007	1
T119	1415	1
T121	2581	2
T122	3680	2
T123	8045	2
T128	2590	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T61
1	0	Covered	T58,T59,T61
1	1	Covered	T61,T136,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T61
1	0	Covered	T61,T136,T132
1	1	Covered	T58,T59,T61

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	32	0	0
SrcPulseCheck_M	555636433	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	32
T58	12228	2
T59	17535	1
T61	5319	2
T62	5794	2
T64	9577	1
T119	5884	2
T120	10137	1
T121	12162	3
T122	3131	1
T123	8577	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	555636433	32
T58	24458	2
T59	17535	1
T61	22166	2
T62	57950	2
T64	10080	1
T119	7355	2
T120	42239	1
T121	12669	3
T122	16484	1
T123	35738	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T61
1	0	Covered	T58,T59,T61
1	1	Covered	T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T58,T59,T61
1	0	Covered	T132
1	1	Covered	T58,T59,T61

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	31	0	0
SrcPulseCheck_M	555636433	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	31
T58	12228	1
T59	17535	1
T61	5319	2
T62	5794	1
T64	9577	1
T119	5884	1
T120	10137	1
T121	12162	2
T122	3131	2
T127	6417	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	555636433	31
T58	24458	1
T59	17535	1
T61	22166	2
T62	57950	1
T64	10080	1
T119	7355	1
T120	42239	1
T121	12669	2
T122	16484	2
T127	13096	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T60,T65,T62
1	0	Covered	T60,T65,T62
1	1	Covered	T62,T128,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T60,T65,T62
1	0	Covered	T62,T128,T130
1	1	Covered	T60,T65,T62

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	33	0	0
SrcPulseCheck_M	266653624	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	33
T60	13684	2
T62	5794	2
T64	9577	1
T65	6014	2
T123	8577	1
T124	5766	1
T125	6593	1
T127	6417	1
T128	12848	3
T137	3680	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	266653624	33
T60	12632	2
T62	27816	2
T64	4839	1
T65	5248	2
T123	17154	1
T124	11071	1
T125	6593	1
T127	6286	1
T128	6166	3
T137	7361	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T60,T65,T62
1	0	Covered	T60,T65,T62
1	1	Covered	T65,T62,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T60,T65,T62
1	0	Covered	T65,T62,T125
1	1	Covered	T60,T65,T62

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163881445	24	0	0
SrcPulseCheck_M	266653624	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163881445	24
T60	13684	2
T62	5794	2
T64	9577	1
T65	6014	2
T123	8577	1
T124	5766	1
T125	6593	2
T128	12848	1
T130	8818	1
T136	9812	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	266653624	24
T60	12632	2
T62	27816	2
T64	4839	1
T65	5248	2
T123	17154	1
T124	11071	1
T125	6593	2
T128	6166	1
T130	8299	1
T136	9420	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	520093574	93337	0	0
SrcPulseCheck_M	20382555	92799	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	520093574	93337
T1	207582	532
T2	0	977
T3	0	939
T4	35055	23
T5	0	156
T7	1841	0
T10	0	509
T11	0	59
T17	2388	0
T18	2479	0
T19	20422	0
T20	3581	0
T21	1304	0
T22	3640	0
T23	2412	0
T24	0	18
T28	0	160
T29	0	32

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20382555	92799
T1	54025	532
T2	0	978
T3	0	840
T4	92	23
T5	0	156
T7	134	0
T10	0	509
T11	0	59
T17	174	0
T18	180	0
T19	1489	0
T20	261	0
T21	95	0
T22	265	0
T23	175	0
T24	0	18
T28	0	160
T29	0	32

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	261294892	92878	0	0
SrcPulseCheck_M	20382555	92344	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	261294892	92878
T1	103391	532
T2	0	977
T3	0	939
T4	17488	23
T5	0	156
T7	868	0
T10	0	503
T11	0	59
T17	1320	0
T18	1220	0
T19	11482	0
T20	1808	0
T21	599	0
T22	1794	0
T23	1266	0
T24	0	18
T28	0	160
T29	0	32

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20382555	92344
T1	54025	532
T2	0	978
T3	0	840
T4	92	23
T5	0	156
T7	134	0
T10	0	503
T11	0	59
T17	174	0
T18	180	0
T19	1489	0
T20	261	0
T21	95	0
T22	265	0
T23	175	0
T24	0	18
T28	0	160
T29	0	32

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	130646752	91986	0	0
SrcPulseCheck_M	20382555	91459	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	130646752	91986
T1	516951	532
T2	0	974
T3	0	938
T4	8744	22
T5	0	156
T7	434	0
T10	0	470
T11	0	59
T17	658	0
T18	610	0
T19	5740	0
T20	904	0
T21	299	0
T22	897	0
T23	632	0
T24	0	18
T28	0	160
T29	0	32

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20382555	91459
T1	54025	532
T2	0	975
T3	0	839
T4	92	22
T5	0	156
T7	134	0
T10	0	470
T11	0	59
T17	174	0
T18	180	0
T19	1489	0
T20	261	0
T21	95	0
T22	265	0
T23	175	0
T24	0	18
T28	0	160
T29	0	32

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	552758290	112557	0	0
SrcPulseCheck_M	20812657	111828	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	552758290	112557
T1	225238	711
T2	0	1143
T3	0	1142
T4	66518	80
T5	0	180
T7	1917	0
T10	0	654
T11	0	35
T17	2487	0
T18	2582	0
T19	21274	0
T20	3730	0
T21	1359	0
T22	3793	0
T23	2513	0
T24	0	18
T28	0	232
T29	0	53

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20812657	111828
T1	54205	711
T2	0	973
T3	0	1142
T4	152	80
T5	0	180
T7	134	0
T10	0	654
T11	0	35
T17	174	0
T18	180	0
T19	1489	0
T20	261	0
T21	95	0
T22	265	0
T23	175	0
T24	0	18
T28	0	232
T29	0	53

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	265272145	110816	0	0
SrcPulseCheck_M	20775305	110770	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	265272145	110816
T1	107252	674
T2	0	1093
T3	0	1199
T4	31928	78
T5	0	156
T7	920	0
T10	0	605
T11	0	47
T17	1194	0
T18	1239	0
T19	10212	0
T20	1790	0
T21	652	0
T22	1820	0
T23	1206	0
T24	0	16
T28	0	232
T29	0	64

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20775305	110770
T1	54169	674
T2	0	1093
T3	0	1199
T4	152	78
T5	0	156
T7	134	0
T10	0	605
T11	0	47
T17	174	0
T18	180	0
T19	1489	0
T20	261	0
T21	95	0
T22	265	0
T23	175	0
T24	0	16
T28	0	232
T29	0	64

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb