Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163881445	5711603	0	0
clk_enables_rd_A	163881445	32528	0	0
clk_hints_rd_A	163881445	28488	0	0
extclk_ctrl_rd_A	163881445	38505	0	0
extclk_ctrl_regwen_rd_A	163881445	27649	0	0
jitter_enable_rd_A	163881445	43151	0	0
jitter_regwen_rd_A	163881445	31015	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	5711603	0	0
T1	224174	66031	0	0
T2	0	59282	0	0
T3	0	178381	0	0
T4	16629	0	0	0
T7	958	0	0	0
T15	0	111441	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0
T38	0	200859	0	0
T39	0	175754	0	0
T66	0	125403	0	0
T67	0	104643	0	0
T68	0	30322	0	0
T69	0	102170	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	32528	0	0
T11	106900	23	0	0
T13	0	4	0	0
T24	10533	0	0	0
T33	18358	0	0	0
T68	0	1195	0	0
T69	0	3850	0	0
T138	0	8	0	0
T139	0	3	0	0
T140	0	2713	0	0
T141	0	2	0	0
T142	0	15	0	0
T143	0	4	0	0
T144	1596	0	0	0
T145	876	0	0	0
T146	2601	0	0	0
T147	1623	0	0	0
T148	2528	0	0	0
T149	1539	0	0	0
T150	3772	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	28488	0	0
T11	106900	13	0	0
T13	0	2	0	0
T24	10533	0	0	0
T33	18358	0	0	0
T68	0	1159	0	0
T69	0	3318	0	0
T138	0	3	0	0
T139	0	6	0	0
T140	0	2648	0	0
T141	0	7	0	0
T142	0	17	0	0
T144	1596	0	0	0
T145	876	0	0	0
T146	2601	0	0	0
T147	1623	0	0	0
T148	2528	0	0	0
T149	1539	0	0	0
T150	3772	0	0	0
T151	0	6	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	38505	0	0
T4	16629	0	0	0
T7	958	10	0	0
T11	0	105	0	0
T17	2487	0	0	0
T18	2557	0	0	0
T19	2126	0	0	0
T20	894	0	0	0
T21	1291	0	0	0
T22	1859	0	0	0
T23	2463	0	0	0
T31	0	56	0	0
T70	2090	0	0	0
T71	0	20	0	0
T75	0	2	0	0
T147	0	4	0	0
T152	0	30	0	0
T153	0	23	0	0
T154	0	24	0	0
T155	0	70	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	27649	0	0
T31	84460	15	0	0
T36	1336	0	0	0
T42	681	0	0	0
T68	0	1155	0	0
T69	0	3611	0	0
T88	1806	0	0	0
T140	0	2562	0	0
T155	2850	0	0	0
T156	0	29	0	0
T157	0	86	0	0
T158	0	26	0	0
T159	0	53	0	0
T160	0	2430	0	0
T161	0	1101	0	0
T162	1464	0	0	0
T163	1495	0	0	0
T164	2161	0	0	0
T165	2330	0	0	0
T166	2377	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	43151	0	0
T2	115961	0	0	0
T11	0	760	0	0
T13	0	112	0	0
T28	98802	0	0	0
T43	2360	63	0	0
T68	0	1616	0	0
T69	0	4638	0	0
T71	1516	0	0	0
T72	1524	0	0	0
T73	1459	0	0	0
T74	2138	0	0	0
T75	1246	0	0	0
T112	1431	0	0	0
T113	1785	0	0	0
T138	0	109	0	0
T139	0	122	0	0
T140	0	3877	0	0
T141	0	119	0	0
T151	0	101	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163881445	31015	0	0
T68	104353	1213	0	0
T69	0	3901	0	0
T91	1778	0	0	0
T140	0	2867	0	0
T160	0	2696	0	0
T161	0	1245	0	0
T167	0	4016	0	0
T168	0	1954	0	0
T169	0	2136	0	0
T170	0	2712	0	0
T171	0	3464	0	0
T172	70956	0	0	0
T173	2481	0	0	0
T174	1781	0	0	0
T175	1481	0	0	0
T176	1833	0	0	0
T177	2314	0	0	0
T178	1440	0	0	0
T179	910	0	0	0