SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T6,T1,T17 |
1 | 1 | Covered | T6,T1,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 520094035 | 4788 | 0 | 0 |
g_div2.Div2Whole_A | 520094035 | 5716 | 0 | 0 |
g_div4.Div4Stepped_A | 261295306 | 4701 | 0 | 0 |
g_div4.Div4Whole_A | 261295306 | 5409 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 520094035 | 4788 | 0 | 0 |
T1 | 207582 | 38 | 0 | 0 |
T4 | 35055 | 0 | 0 | 0 |
T6 | 7391 | 8 | 0 | 0 |
T7 | 1841 | 1 | 0 | 0 |
T17 | 2388 | 9 | 0 | 0 |
T18 | 2479 | 0 | 0 | 0 |
T19 | 20423 | 11 | 0 | 0 |
T20 | 3582 | 1 | 0 | 0 |
T21 | 1305 | 0 | 0 | 0 |
T22 | 3641 | 0 | 0 | 0 |
T23 | 0 | 5 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T113 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 520094035 | 5716 | 0 | 0 |
T1 | 207582 | 58 | 0 | 0 |
T4 | 35055 | 0 | 0 | 0 |
T6 | 7391 | 8 | 0 | 0 |
T7 | 1841 | 1 | 0 | 0 |
T17 | 2388 | 11 | 0 | 0 |
T18 | 2479 | 0 | 0 | 0 |
T19 | 20423 | 12 | 0 | 0 |
T20 | 3582 | 1 | 0 | 0 |
T21 | 1305 | 0 | 0 | 0 |
T22 | 3641 | 0 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T70 | 0 | 14 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261295306 | 4701 | 0 | 0 |
T1 | 103391 | 37 | 0 | 0 |
T4 | 17488 | 0 | 0 | 0 |
T6 | 4043 | 8 | 0 | 0 |
T7 | 869 | 1 | 0 | 0 |
T17 | 1321 | 7 | 0 | 0 |
T18 | 1221 | 0 | 0 | 0 |
T19 | 11482 | 11 | 0 | 0 |
T20 | 1808 | 1 | 0 | 0 |
T21 | 599 | 0 | 0 | 0 |
T22 | 1795 | 0 | 0 | 0 |
T23 | 0 | 5 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T113 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261295306 | 5409 | 0 | 0 |
T1 | 103391 | 45 | 0 | 0 |
T4 | 17488 | 0 | 0 | 0 |
T6 | 4043 | 8 | 0 | 0 |
T7 | 869 | 1 | 0 | 0 |
T17 | 1321 | 9 | 0 | 0 |
T18 | 1221 | 0 | 0 | 0 |
T19 | 11482 | 12 | 0 | 0 |
T20 | 1808 | 1 | 0 | 0 |
T21 | 599 | 0 | 0 | 0 |
T22 | 1795 | 0 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T70 | 0 | 14 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T6,T1,T17 |
1 | 1 | Covered | T6,T1,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 520094035 | 4788 | 0 | 0 |
g_div2.Div2Whole_A | 520094035 | 5716 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 520094035 | 4788 | 0 | 0 |
T1 | 207582 | 38 | 0 | 0 |
T4 | 35055 | 0 | 0 | 0 |
T6 | 7391 | 8 | 0 | 0 |
T7 | 1841 | 1 | 0 | 0 |
T17 | 2388 | 9 | 0 | 0 |
T18 | 2479 | 0 | 0 | 0 |
T19 | 20423 | 11 | 0 | 0 |
T20 | 3582 | 1 | 0 | 0 |
T21 | 1305 | 0 | 0 | 0 |
T22 | 3641 | 0 | 0 | 0 |
T23 | 0 | 5 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T113 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 520094035 | 5716 | 0 | 0 |
T1 | 207582 | 58 | 0 | 0 |
T4 | 35055 | 0 | 0 | 0 |
T6 | 7391 | 8 | 0 | 0 |
T7 | 1841 | 1 | 0 | 0 |
T17 | 2388 | 11 | 0 | 0 |
T18 | 2479 | 0 | 0 | 0 |
T19 | 20423 | 12 | 0 | 0 |
T20 | 3582 | 1 | 0 | 0 |
T21 | 1305 | 0 | 0 | 0 |
T22 | 3641 | 0 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T70 | 0 | 14 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T6,T1,T17 |
1 | 1 | Covered | T6,T1,T7 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 261295306 | 4701 | 0 | 0 |
g_div4.Div4Whole_A | 261295306 | 5409 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261295306 | 4701 | 0 | 0 |
T1 | 103391 | 37 | 0 | 0 |
T4 | 17488 | 0 | 0 | 0 |
T6 | 4043 | 8 | 0 | 0 |
T7 | 869 | 1 | 0 | 0 |
T17 | 1321 | 7 | 0 | 0 |
T18 | 1221 | 0 | 0 | 0 |
T19 | 11482 | 11 | 0 | 0 |
T20 | 1808 | 1 | 0 | 0 |
T21 | 599 | 0 | 0 | 0 |
T22 | 1795 | 0 | 0 | 0 |
T23 | 0 | 5 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 0 | 5 | 0 | 0 |
T113 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261295306 | 5409 | 0 | 0 |
T1 | 103391 | 45 | 0 | 0 |
T4 | 17488 | 0 | 0 | 0 |
T6 | 4043 | 8 | 0 | 0 |
T7 | 869 | 1 | 0 | 0 |
T17 | 1321 | 9 | 0 | 0 |
T18 | 1221 | 0 | 0 | 0 |
T19 | 11482 | 12 | 0 | 0 |
T20 | 1808 | 1 | 0 | 0 |
T21 | 599 | 0 | 0 | 0 |
T22 | 1795 | 0 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T70 | 0 | 14 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 8 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |