Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	488922042	389	0	0
StatusRise_A	488922042	389	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488922042	389	0	0
T10	254538	0	0	0
T34	5856	0	0	0
T40	2637	8	0	0
T41	3480	9	0	0
T42	0	7	0	0
T114	3591	0	0	0
T152	4488	0	0	0
T153	4047	0	0	0
T154	4143	0	0	0
T180	0	6	0	0
T181	0	13	0	0
T182	0	9	0	0
T183	0	1	0	0
T184	0	3	0	0
T185	0	7	0	0
T186	0	6	0	0
T187	0	4	0	0
T188	2169	0	0	0
T189	3813	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488922042	389	0	0
T10	254538	0	0	0
T34	5856	0	0	0
T40	2637	8	0	0
T41	3480	9	0	0
T42	0	7	0	0
T114	3591	0	0	0
T152	4488	0	0	0
T153	4047	0	0	0
T154	4143	0	0	0
T180	0	6	0	0
T181	0	13	0	0
T182	0	9	0	0
T183	0	1	0	0
T184	0	3	0	0
T185	0	7	0	0
T186	0	6	0	0
T187	0	4	0	0
T188	2169	0	0	0
T189	3813	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162974014	130	0	0
StatusRise_A	162974014	130	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	130	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	4	0	0
T41	1160	3	0	0
T42	0	2	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T186	0	3	0	0
T187	0	2	0	0
T188	723	0	0	0
T189	1271	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	130	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	4	0	0
T41	1160	3	0	0
T42	0	2	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T186	0	3	0	0
T187	0	2	0	0
T188	723	0	0	0
T189	1271	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162974014	128	0	0
StatusRise_A	162974014	128	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	128	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	2	0	0
T41	1160	3	0	0
T42	0	2	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	1	0	0
T188	723	0	0	0
T189	1271	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	128	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	2	0	0
T41	1160	3	0	0
T42	0	2	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	1	0	0
T188	723	0	0	0
T189	1271	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162974014	131	0	0
StatusRise_A	162974014	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	131	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	2	0	0
T41	1160	3	0	0
T42	0	3	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	723	0	0	0
T189	1271	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162974014	131	0	0
T10	84846	0	0	0
T34	1952	0	0	0
T40	879	2	0	0
T41	1160	3	0	0
T42	0	3	0	0
T114	1197	0	0	0
T152	1496	0	0	0
T153	1349	0	0	0
T154	1381	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	723	0	0	0
T189	1271	0	0	0