Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50926	0	0
CgEnOn_A	2147483647	41641	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50926	0	0
T1	1053162	293	0	0
T3	2029817	109	0	0
T4	127805	3	0	0
T6	13454	3	0	0
T7	5060	3	0	0
T17	6853	3	0	0
T18	6891	10	0	0
T19	58918	3	0	0
T20	10023	3	0	0
T21	3561	3	0	0
T22	10124	7	0	0
T23	2513	0	0	0
T29	77733	0	0	0
T30	75594	0	0	0
T38	0	5	0	0
T40	8671	14	0	0
T41	4497	15	0	0
T42	0	10	0	0
T77	4432	0	0	0
T78	40924	0	0	0
T87	0	3	0	0
T152	13237	0	0	0
T180	0	10	0	0
T181	0	15	0	0
T182	0	15	0	0
T183	0	5	0	0
T184	0	5	0	0
T190	5535	0	0	0
T191	8801	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41641	0	0
T1	620342	281	0	0
T2	0	199	0	0
T3	1888722	500	0	0
T4	26232	0	0	0
T7	1302	0	0	0
T17	1978	0	0	0
T18	1830	7	0	0
T19	17222	0	0	0
T20	2712	0	0	0
T21	898	0	0	0
T22	2691	4	0	0
T23	1898	0	0	0
T29	43171	0	0	0
T30	31265	0	0	0
T38	0	5	0	0
T40	8671	20	0	0
T41	4497	24	0	0
T42	0	10	0	0
T43	0	4	0	0
T73	0	2	0	0
T77	2498	0	0	0
T78	22820	11	0	0
T87	0	3	0	0
T114	4601	0	0	0
T152	13237	0	0	0
T180	0	10	0	0
T181	0	15	0	0
T182	0	15	0	0
T183	0	5	0	0
T184	0	5	0	0
T185	0	2	0	0
T188	0	22	0	0
T190	3054	7	0	0
T191	5196	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	261294892	136	0	0
CgEnOn_A	261294892	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261294892	136	0	0
T3	755490	2	0	0
T29	17269	0	0	0
T30	12506	0	0	0
T38	0	1	0	0
T40	1921	2	0	0
T41	994	3	0	0
T42	0	2	0	0
T77	1001	0	0	0
T78	9128	0	0	0
T152	3086	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	1221	0	0	0
T191	2082	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261294892	136	0	0
T3	755490	2	0	0
T29	17269	0	0	0
T30	12506	0	0	0
T38	0	1	0	0
T40	1921	2	0	0
T41	994	3	0	0
T42	0	2	0	0
T77	1001	0	0	0
T78	9128	0	0	0
T152	3086	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	1221	0	0	0
T191	2082	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130646752	136	0	0
CgEnOn_A	130646752	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130646752	136	0	0
CgEnOn_A	130646752	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130646752	136	0	0
CgEnOn_A	130646752	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	136	0	0
T3	377744	2	0	0
T29	8634	0	0	0
T30	6253	0	0	0
T38	0	1	0	0
T40	961	2	0	0
T41	497	3	0	0
T42	0	2	0	0
T77	499	0	0	0
T78	4564	0	0	0
T152	1542	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	611	0	0	0
T191	1038	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	520093574	136	0	0
CgEnOn_A	520093574	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520093574	136	0	0
T3	141095	2	0	0
T29	34562	0	0	0
T30	44329	0	0	0
T38	0	1	0	0
T40	3867	2	0	0
T41	2012	3	0	0
T42	0	2	0	0
T77	1934	0	0	0
T78	18104	0	0	0
T152	5525	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T190	2481	0	0	0
T191	3605	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520093574	130	0	0
T10	625252	0	0	0
T34	7811	0	0	0
T38	0	1	0	0
T40	3867	2	0	0
T41	2012	3	0	0
T42	0	2	0	0
T114	4601	0	0	0
T152	5525	0	0	0
T153	9256	0	0	0
T154	5308	0	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T188	4630	0	0	0
T189	5087	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	137	0	0
CgEnOn_A	552758290	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	137	0	0
T2	461609	1	0	0
T3	148044	0	0	0
T29	48004	0	0	0
T30	46177	0	0	0
T38	0	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T42	0	2	0	0
T74	2138	0	0	0
T75	1246	0	0	0
T76	3908	0	0	0
T77	2014	0	0	0
T78	18860	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T190	2585	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	133	0	0
T10	747323	0	0	0
T34	8138	0	0	0
T38	0	1	0	0
T40	4340	4	0	0
T41	2072	3	0	0
T42	0	2	0	0
T114	4793	0	0	0
T152	5755	0	0	0
T153	9642	0	0	0
T154	5529	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T186	0	3	0	0
T188	4823	0	0	0
T189	5300	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	137	0	0
CgEnOn_A	552758290	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	137	0	0
T2	461609	1	0	0
T3	148044	0	0	0
T29	48004	0	0	0
T30	46177	0	0	0
T38	0	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T42	0	2	0	0
T74	2138	0	0	0
T75	1246	0	0	0
T76	3908	0	0	0
T77	2014	0	0	0
T78	18860	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T190	2585	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	133	0	0
T10	747323	0	0	0
T34	8138	0	0	0
T38	0	1	0	0
T40	4340	4	0	0
T41	2072	3	0	0
T42	0	2	0	0
T114	4793	0	0	0
T152	5755	0	0	0
T153	9642	0	0	0
T154	5529	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0
T186	0	3	0	0
T188	4823	0	0	0
T189	5300	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	265272145	132	0	0
CgEnOn_A	265272145	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272145	132	0	0
T10	350079	0	0	0
T34	3906	0	0	0
T40	1976	2	0	0
T41	947	3	0	0
T42	0	3	0	0
T114	2300	0	0	0
T152	2762	0	0	0
T153	4628	0	0	0
T154	2654	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	2315	0	0	0
T189	2543	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272145	131	0	0
T10	350079	0	0	0
T34	3906	0	0	0
T40	1976	2	0	0
T41	947	3	0	0
T42	0	3	0	0
T114	2300	0	0	0
T152	2762	0	0	0
T153	4628	0	0	0
T154	2654	0	0	0
T180	0	2	0	0
T181	0	5	0	0
T182	0	3	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	2315	0	0	0
T189	2543	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130646752	8123	0	0
CgEnOn_A	130646752	5813	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	8123	0	0
T1	516951	86	0	0
T4	8744	1	0	0
T6	2021	1	0	0
T7	434	1	0	0
T17	658	1	0	0
T18	610	1	0	0
T19	5740	1	0	0
T20	904	1	0	0
T21	299	1	0	0
T22	897	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130646752	5813	0	0
T1	516951	82	0	0
T2	0	55	0	0
T3	0	132	0	0
T4	8744	0	0	0
T7	434	0	0	0
T17	658	0	0	0
T18	610	0	0	0
T19	5740	0	0	0
T20	904	0	0	0
T21	299	0	0	0
T22	897	1	0	0
T23	632	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	2	0	0
T188	0	8	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	261294892	8199	0	0
CgEnOn_A	261294892	5889	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261294892	8199	0	0
T1	103391	83	0	0
T4	17488	1	0	0
T6	4042	1	0	0
T7	868	1	0	0
T17	1320	1	0	0
T18	1220	1	0	0
T19	11482	1	0	0
T20	1808	1	0	0
T21	599	1	0	0
T22	1794	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261294892	5889	0	0
T1	103391	79	0	0
T2	0	58	0	0
T3	0	131	0	0
T4	17488	0	0	0
T7	868	0	0	0
T17	1320	0	0	0
T18	1220	0	0	0
T19	11482	0	0	0
T20	1808	0	0	0
T21	599	0	0	0
T22	1794	1	0	0
T23	1266	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	2	0	0
T188	0	7	0	0
T190	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	520093574	8217	0	0
CgEnOn_A	520093574	5901	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520093574	8217	0	0
T1	207582	85	0	0
T4	35055	1	0	0
T6	7391	1	0	0
T7	1841	1	0	0
T17	2388	1	0	0
T18	2479	1	0	0
T19	20422	1	0	0
T20	3581	1	0	0
T21	1304	1	0	0
T22	3640	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520093574	5901	0	0
T1	207582	81	0	0
T2	0	56	0	0
T3	0	130	0	0
T4	35055	0	0	0
T7	1841	0	0	0
T17	2388	0	0	0
T18	2479	0	0	0
T19	20422	0	0	0
T20	3581	0	0	0
T21	1304	0	0	0
T22	3640	1	0	0
T23	2412	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	2	0	0
T188	0	7	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	265272145	8201	0	0
CgEnOn_A	265272145	5883	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272145	8201	0	0
T1	107252	85	0	0
T4	31928	1	0	0
T6	3696	1	0	0
T7	920	1	0	0
T17	1194	1	0	0
T18	1239	1	0	0
T19	10212	1	0	0
T20	1790	1	0	0
T21	652	1	0	0
T22	1820	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272145	5883	0	0
T1	107252	81	0	0
T2	0	59	0	0
T3	0	130	0	0
T4	31928	0	0	0
T7	920	0	0	0
T17	1194	0	0	0
T18	1239	0	0	0
T19	10212	0	0	0
T20	1790	0	0	0
T21	652	0	0	0
T22	1820	1	0	0
T23	1206	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	2	0	0
T188	0	6	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T22
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	4174	0	0
CgEnOn_A	552758290	4170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4174	0	0
T1	225238	39	0	0
T2	0	31	0	0
T3	0	99	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	7	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	2	0	0
T78	0	5	0	0
T87	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4170	0	0
T1	225238	39	0	0
T2	0	30	0	0
T3	0	99	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	7	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	2	0	0
T78	0	5	0	0
T87	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T22
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	4330	0	0
CgEnOn_A	552758290	4326	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4330	0	0
T1	225238	34	0	0
T2	0	38	0	0
T3	0	98	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	9	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	5	0	0
T87	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4326	0	0
T1	225238	34	0	0
T2	0	37	0	0
T3	0	98	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	9	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	5	0	0
T87	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T22
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	4271	0	0
CgEnOn_A	552758290	4267	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4271	0	0
T1	225238	37	0	0
T2	0	37	0	0
T3	0	92	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	8	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	4	0	0
T87	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4267	0	0
T1	225238	37	0	0
T2	0	36	0	0
T3	0	92	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	8	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	4	0	0
T87	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T22
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	552758290	4325	0	0
CgEnOn_A	552758290	4321	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4325	0	0
T1	225238	38	0	0
T2	0	36	0	0
T3	0	103	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	11	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	3	0	0
T87	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552758290	4321	0	0
T1	225238	38	0	0
T2	0	35	0	0
T3	0	103	0	0
T4	66518	0	0	0
T7	1917	0	0	0
T17	2487	0	0	0
T18	2582	11	0	0
T19	21274	0	0	0
T20	3730	0	0	0
T21	1359	0	0	0
T22	3793	1	0	0
T23	2513	0	0	0
T40	0	4	0	0
T43	0	1	0	0
T73	0	3	0	0
T78	0	3	0	0
T87	0	3	0	0