Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323828810 1 T6 2886 T7 4746 T8 3586
auto[1] 424800 1 T8 704 T23 146 T1 4908


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323822860 1 T6 2886 T7 4746 T8 3708
auto[1] 430750 1 T8 582 T23 142 T1 3552


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323724678 1 T6 2886 T7 4746 T8 3776
auto[1] 528932 1 T8 514 T23 142 T1 4644


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 305781564 1 T6 2886 T7 4746 T8 2854
auto[1] 18472046 1 T8 1436 T23 1970 T1 13674


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 184868892 1 T6 2886 T7 3910 T8 3858
auto[1] 139384718 1 T7 836 T8 432 T23 176


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 172987408 1 T6 2886 T7 3910 T8 2420
auto[0] auto[0] auto[0] auto[0] auto[1] 132434774 1 T7 836 T8 84 T23 80
auto[0] auto[0] auto[0] auto[1] auto[0] 32784 1 T8 46 T1 430 T22 80
auto[0] auto[0] auto[0] auto[1] auto[1] 9012 1 T1 134 T10 40 T152 12
auto[0] auto[0] auto[1] auto[0] auto[0] 11275096 1 T8 784 T23 1884 T1 5534
auto[0] auto[0] auto[1] auto[0] auto[1] 6824886 1 T8 150 T1 3956 T22 1556
auto[0] auto[0] auto[1] auto[1] auto[0] 51188 1 T8 18 T23 40 T1 534
auto[0] auto[0] auto[1] auto[1] auto[1] 13774 1 T8 8 T1 246 T97 4
auto[0] auto[1] auto[0] auto[0] auto[0] 39206 1 T8 40 T1 78 T99 60
auto[0] auto[1] auto[0] auto[0] auto[1] 1708 1 T22 46 T10 4 T153 22
auto[0] auto[1] auto[0] auto[1] auto[0] 12308 1 T8 44 T1 112 T79 118
auto[0] auto[1] auto[0] auto[1] auto[1] 2844 1 T10 52 T14 158 T15 82
auto[0] auto[1] auto[1] auto[0] auto[0] 11440 1 T8 8 T1 62 T22 52
auto[0] auto[1] auto[1] auto[0] auto[1] 2814 1 T8 10 T1 14 T97 20
auto[0] auto[1] auto[1] auto[1] auto[0] 19928 1 T8 102 T1 224 T22 88
auto[0] auto[1] auto[1] auto[1] auto[1] 5508 1 T8 62 T1 126 T97 60
auto[1] auto[0] auto[0] auto[0] auto[0] 42054 1 T8 2 T1 64 T22 26
auto[1] auto[0] auto[0] auto[0] auto[1] 4870 1 T1 38 T19 34 T22 40
auto[1] auto[0] auto[0] auto[1] auto[0] 31834 1 T8 52 T1 234 T22 144
auto[1] auto[0] auto[0] auto[1] auto[1] 8264 1 T1 70 T22 76 T10 68
auto[1] auto[0] auto[1] auto[0] auto[0] 31430 1 T8 52 T1 452 T19 60
auto[1] auto[0] auto[1] auto[0] auto[1] 7340 1 T1 40 T22 50 T10 78
auto[1] auto[0] auto[1] auto[1] auto[0] 54834 1 T8 92 T1 516 T22 126
auto[1] auto[0] auto[1] auto[1] auto[1] 13312 1 T1 294 T10 130 T154 54
auto[1] auto[1] auto[0] auto[0] auto[0] 101812 1 T8 4 T1 380 T19 48
auto[1] auto[1] auto[0] auto[0] auto[1] 7478 1 T8 2 T23 34 T1 54
auto[1] auto[1] auto[0] auto[1] auto[0] 51116 1 T8 104 T1 756 T22 280
auto[1] auto[1] auto[0] auto[1] auto[1] 14092 1 T8 56 T23 62 T1 70
auto[1] auto[1] auto[1] auto[0] auto[0] 44718 1 T8 28 T23 2 T1 408
auto[1] auto[1] auto[1] auto[0] auto[1] 11776 1 T8 2 T1 106 T22 68
auto[1] auto[1] auto[1] auto[1] auto[0] 81736 1 T8 62 T23 44 T1 784
auto[1] auto[1] auto[1] auto[1] auto[1] 22266 1 T8 58 T1 378 T22 56

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