---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	173334352	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12595371	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	86666551	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12595371	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	348369267	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12595371	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	372807150	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12595371	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	174712227	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	87355486	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	351218874	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	375775600	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	180356478	0	0	1010
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	178931655	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	12595371	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	163925371	161278095	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	163925371	161278095	0	0
tb.dut.CgEnKnownO_A	0	0	163925371	161278095	0	0
tb.dut.ClocksKownO_A	0	0	163925371	161278095	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	163925371	47	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	163925371	41	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	163925371	46	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	163925371	44	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	163925371	90	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	163925371	161278095	0	0
tb.dut.JitterEnableKnownO_A	0	0	163925371	161278095	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	163925371	161278095	0	0
tb.dut.PwrMgrKnownO_A	0	0	163925371	161278095	0	0
tb.dut.TlAReadyKnownO_A	0	0	163925371	161278095	0	0
tb.dut.TlDValidKnownO_A	0	0	163925371	161278095	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	372807597	3439	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	372807597	1809	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	173334352	168	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	173334352	168	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	173334352	7242	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	173334352	4823	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	86666551	7215	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	86666551	4796	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	86666551	168	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	348369267	168	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	348369267	160	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	348369267	7268	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	348369267	4841	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	372807150	3597	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	372807150	3594	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	372807150	3630	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	372807150	3627	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	372807150	158	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	372807150	155	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	372807150	3784	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	372807150	3781	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	372807150	3602	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	372807150	3599	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	372807150	158	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	372807150	155	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A	0	0	178931655	164	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A	0	0	178931655	162	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	178931655	7276	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	178931655	4848	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	164868292	5293800	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	164868292	45450	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	164868292	39583	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	164868292	49645	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	164868292	37105	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	164868292	54204	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	164868292	41275	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	348369730	4299	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	348369730	5185	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	173334766	4210	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	173334766	4841	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	163925371	4062	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	163925371	4062	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	163925371	2412	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	163925371	2412	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	163925371	5131	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	163925371	5131	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	372807597	3472	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	372807597	1794	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	173334766	3164	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	173334766	4917	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	86666959	2942	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	86666959	4695	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	348369730	3169	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	348369730	4924	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	372807597	3626	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	372807597	1879	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	163925371	11963	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	163925371	16676	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	163925371	25836	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	163925371	11799	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	163925371	19338905	0	58
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	163925371	16640	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	372807597	3444	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	372807597	1797	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	163925371	159	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	163925371	159	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	163925371	154	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	163925371	154	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	163925371	162	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	163925371	162	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	163925371	161141961	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	163925371	133706	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	163925371	161058411	0	2415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	163925371	212400	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	163925371	161151031	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	163925371	124636	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	178932052	3152	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	178932052	4908	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	164868292	20538578	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	164868292	162126805	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	164868292	162126805	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	164868292	20625527	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	164868292	162126805	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	164868292	162126805	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
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tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	164868923	16917294	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	164868292	2851224	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	164868923	228571	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	164868923	148194	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	164868292	3152971	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	164868923	20538578	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	164868923	20625527	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	164868923	20538578	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	164868923	20625527	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	164868923	20625527	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	164868923	20625527	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	164868292	1703969	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	164868292	1299111	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1010	1010	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	372807150	30596	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	372807150	30536	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	372807150	30757	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	372807150	30511	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372807150	368164639	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	163925371	19200	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	163925371	16906	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	163925371	2838	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	173334352	2838	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	173334352	2787504	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	173334352	89024	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	12424417	88674	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	173334352	173334352	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	173334352	173334352	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	163925371	2824	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	86666551	2824	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	86666551	2656930	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	86666551	88114	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	12424417	87774	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	86666551	86666551	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	86666551	86666551	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	163925371	2806	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	348369267	2806	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	348369267	2787610	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	348369267	89552	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	12424417	89193	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	348369267	346162412	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	348369267	346162412	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	348369267	343952474	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	348369267	343945190	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	348369267	27025	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	163925371	2824	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	372807150	2824	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	372807150	2791417	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	372807150	106821	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	11945827	106458	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	372807150	370485106	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372807150	370485106	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	173081788	173080983	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	348369267	348368462	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	173334352	173333547	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	348369267	348368462	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	86666551	86665746	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	348369267	348368462	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	173334352	172228894	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	173334352	172228894	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	86666551	86113888	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	86666551	86113888	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	86666551	86113888	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	86666551	86113888	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	348369267	343952474	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	348369267	343952474	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	372807150	368164639	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	178931655	176703991	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	178931655	176703991	0	0
tb.dut.u_reg.en2addrHit	0	0	164868292	819219	0	0
tb.dut.u_reg.reAfterRv	0	0	164868292	819219	0	0
tb.dut.u_reg.rePulse	0	0	164868292	194837	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	164868292	137350	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	174712227	173559216	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	174712227	1174	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	164868292	25182	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	174712227	24006	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	174712227	24008	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	164868292	172347	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	174712227	173559216	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	164868292	30553	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	164868292	30551	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	174712227	30559	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	174712227	30557	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	30586	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	174712227	173559216	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	164868292	41	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	174712227	41	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	174712227	173559216	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	164868292	38	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	174712227	38	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	164868292	224941	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	87355486	86779082	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	87355486	1174	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	164868292	25182	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	87355486	23967	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	87355486	24008	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	164868292	281104	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	87355486	86779082	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	164868292	30435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	164868292	30433	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	87355486	30441	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	87355486	30435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	30470	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	87355486	86779082	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	164868292	31	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	87355486	31	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	87355486	86779082	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	164868292	36	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	87355486	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	164868292	93531	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	351218874	346613129	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	351218874	1174	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	164868292	25182	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	351218874	24008	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	351218874	24008	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	24008	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	164868292	117370	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	351218874	346613129	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	164868292	30444	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	164868292	30443	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	351218874	30462	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	351218874	30459	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	30473	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	351218874	346613129	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	164868292	39	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	351218874	39	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	351218874	346613129	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	164868292	39	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	351218874	39	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	164868292	91949	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	375775600	370936223	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	164868292	24008	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	375775600	1174	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	164868292	25182	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	375775600	24008	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	375775600	24008	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	24008	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	164868292	114838	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	375775600	370936223	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	164868292	30415	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	164868292	30414	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	375775600	30429	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	375775600	30423	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	30441	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	375775600	370936223	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	164868292	25	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	375775600	25	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	375775600	370936223	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	164868292	29	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	375775600	29	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	164868292	134755	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	180356478	178034390	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	164868292	23512	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	180356478	1174	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	164868292	24686	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	180356478	23402	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	180356478	23554	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	24008	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	164868292	171845	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	180356478	178034390	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	164868292	30418	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	164868292	162126805	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	164868292	30397	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	180356478	30539	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	180356478	30508	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	164868292	30702	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	180356478	178034390	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	164868292	45	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	180356478	45	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	180356478	178034390	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	164868292	34	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	180356478	34	0	0
tb.dut.u_reg.wePulse	0	0	164868292	624382	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	163925371	161278095	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	163925371	2603	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	178931655	2603	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	178931655	2791341	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	178931655	105596	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	12453125	104962	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	178931655	177818069	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	178931655	177818069	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	163925371	19338905	0	58
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	163925371	161058411	0	2415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	372807150	368157315	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	348369267	343945190	0	2415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	174712227	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	87355486	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	351218874	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	375775600	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	180356478	0	0	1010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	163925371	161270659	0	2415

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	164868923	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	164868923	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	164868923	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	164868923	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	164868923	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	164868923	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	164868923	9025	9025	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	164868923	2238	2238	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	164868923	9320	9320	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	164868923	100355	100355	758

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	164868923	9025	9025	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	164868923	2238	2238	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	164868923	9320	9320	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	164868923	100355	100355	758