Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total694010
Category 0694010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total694010
Severity 0694010


Summary for Assertions
NUMBERPERCENT
Total Number694100.00
Uncovered152.16
Success67997.84
Failure00.00
Incomplete223.17
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered660.00
All Matches440.00
First Matches440.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A 00173334352000
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 0012595371000
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A 0086666551000
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 0012595371000
tb.dut.u_io_meas.u_meas.MaxWidth_A 00348369267000
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 0012595371000
tb.dut.u_main_meas.u_meas.MaxWidth_A 00372807150000
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 0012595371000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00174712227001010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0087355486001010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00351218874001010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00375775600001010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00180356478001010
tb.dut.u_usb_meas.u_meas.MaxWidth_A 00178931655000
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq 0012595371000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 0016392537116127809500
tb.dut.AllClkBypReqKnownO_A 0016392537116127809500
tb.dut.CgEnKnownO_A 0016392537116127809500
tb.dut.ClocksKownO_A 0016392537116127809500
tb.dut.FpvSecCmClkMainAesCountCheck_A 001639253714700
tb.dut.FpvSecCmClkMainHmacCountCheck_A 001639253714100
tb.dut.FpvSecCmClkMainKmacCountCheck_A 001639253714600
tb.dut.FpvSecCmClkMainOtbnCountCheck_A 001639253714400
tb.dut.FpvSecCmRegWeOnehotCheck_A 001639253719000
tb.dut.IoClkBypReqKnownO_A 0016392537116127809500
tb.dut.JitterEnableKnownO_A 0016392537116127809500
tb.dut.LcCtrlClkBypAckKnownO_A 0016392537116127809500
tb.dut.PwrMgrKnownO_A 0016392537116127809500
tb.dut.TlAReadyKnownO_A 0016392537116127809500
tb.dut.TlDValidKnownO_A 0016392537116127809500
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A 00372807597343900
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A 00372807597180900
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A 0080580500
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A 0080580500
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A 0017333435216800
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A 0017333435216800
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A 00173334352724200
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A 00173334352482300
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A 008666655116800
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A 008666655116800
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A 0086666551721500
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A 0086666551479600
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A 008666655116800
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A 008666655116800
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A 008666655116800
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A 008666655116800
tb.dut.clkmgr_cg_io_infra.CgEnOff_A 0034836926716800
tb.dut.clkmgr_cg_io_infra.CgEnOn_A 0034836926716000
tb.dut.clkmgr_cg_io_peri.CgEnOff_A 00348369267726800
tb.dut.clkmgr_cg_io_peri.CgEnOn_A 00348369267484100
tb.dut.clkmgr_cg_main_aes.CgEnOff_A 00372807150359700
tb.dut.clkmgr_cg_main_aes.CgEnOn_A 00372807150359400
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A 00372807150363000
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A 00372807150362700
tb.dut.clkmgr_cg_main_infra.CgEnOff_A 0037280715015800
tb.dut.clkmgr_cg_main_infra.CgEnOn_A 0037280715015500
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A 00372807150378400
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A 00372807150378100
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A 00372807150360200
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A 00372807150359900
tb.dut.clkmgr_cg_main_secure.CgEnOff_A 0037280715015800
tb.dut.clkmgr_cg_main_secure.CgEnOn_A 0037280715015500
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A 0017893165516400
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A 0017893165516200
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A 00178931655727600
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A 00178931655484800
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A 00164868292529380000
tb.dut.clkmgr_csr_assert.clk_enables_rd_A 001648682924545000
tb.dut.clkmgr_csr_assert.clk_hints_rd_A 001648682923958300
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A 001648682924964500
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A 001648682923710500
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A 001648682925420400
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A 001648682924127500
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A 00348369730429900
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A 00348369730518500
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A 00173334766421000
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A 00173334766484100
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A 00163925371406200
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A 00163925371406200
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A 00163925371241200
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A 00163925371241200
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A 00163925371513100
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A 00163925371513100
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A 00372807597347200
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A 00372807597179400
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A 00173334766316400
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A 00173334766491700
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A 0086666959294200
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A 0086666959469500
tb.dut.clkmgr_io_peri_sva_if.GateClose_A 00348369730316900
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A 00348369730492400
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A 00372807597362600
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A 00372807597187900
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A 001639253711196300
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A 001639253711667600
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A 001639253712583600
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A 001639253711179900
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A 0016392537119338905058
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A 001639253711664000
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A 00372807597344400
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A 00372807597179700
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A 0016392537115900
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A 0016392537115900
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A 0016392537115400
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A 0016392537115400
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A 0016392537116200
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A 0016392537116200
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A 0016392537116114196100
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A 0016392537113370600
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A 0016392537116105841102415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A 0016392537121240000
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A 0016392537116115103100
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A 0016392537112463600
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A 00178932052315200
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A 00178932052490800
tb.dut.tlul_assert_device.aKnown_A 001648682922053857800
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0016486829216212680500
tb.dut.tlul_assert_device.aReadyKnown_A 0016486829216212680500
tb.dut.tlul_assert_device.dKnown_A 001648682922062552700
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0016486829216212680500
tb.dut.tlul_assert_device.dReadyKnown_A 0016486829216212680500
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001010101000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001648689231691729400
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 00164868292285122400
tb.dut.tlul_assert_device.gen_device.contigMask_M 0016486892322857100
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 0016486892314819400
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 00164868292315297100
tb.dut.tlul_assert_device.gen_device.legalAParam_M 001648689232053857800
tb.dut.tlul_assert_device.gen_device.legalDParam_A 001648689232062552700
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 001648689232053857800
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 001648689232062552700
tb.dut.tlul_assert_device.gen_device.respOpcode_A 001648689232062552700
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 001648689232062552700
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 00164868292170396900
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00164868292129911100
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 001010101000
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 003728071503059600
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0037280715036816463900
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 003728071503053600
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0037280715036816463900
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 003728071503075700
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0037280715036816463900
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 003728071503051100
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A 0037280715036816463900
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A 0037280715036816463900
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 001639253711920000
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 001639253711690600
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A 0016392537116127809500
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq 00163925371283800
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq 00173334352283800
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A 0080580500
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00173334352278750400
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A 0080580500
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A 001733343528902400
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M 00124244178867400
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A 0017333435217333435200
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0017333435217333435200
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A 0016392537116127809500
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq 00163925371282400
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq 0086666551282400
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A 0080580500
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 0086666551265693000
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A 0080580500
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A 00866665518811400
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M 00124244178777400
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A 00866665518666655100
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 00866665518666655100
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq 00163925371280600
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq 00348369267280600
tb.dut.u_io_meas.u_meas.RefCntVal_A 0080580500
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00348369267278761000
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A 0080580500
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A 003483692678955200
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M 00124244178919300
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A 0034836926734616241200
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0034836926734616241200
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_io_step_down_req_sync.OutputsKnown_A 0034836926734395247400
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A 0034836926734394519002415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A 003483692672702500
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq 00163925371282400
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq 00372807150282400
tb.dut.u_main_meas.u_meas.RefCntVal_A 0080580500
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00372807150279141700
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A 0080580500
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A 0037280715010682100
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M 001194582710645800
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A 0037280715037048510600
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0037280715037048510600
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A 0080580500
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0 0017308178817308098300
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1 0034836926734836846200
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0 0017333435217333354700
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1 0034836926734836846200
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A 0080580500
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0 00866665518666574600
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1 0034836926734836846200
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A 0017333435217222889400
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A 0017333435217222889400
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A 00866665518611388800
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A 00866665518611388800
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A 00866665518611388800
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A 00866665518611388800
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A 0034836926734395247400
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A 0034836926734395247400
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A 0037280715036816463900
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A 0037280715036816463900
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A 0017893165517670399100
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A 0017893165517670399100
tb.dut.u_reg.en2addrHit 0016486829281921900
tb.dut.u_reg.reAfterRv 0016486829281921900
tb.dut.u_reg.rePulse 0016486829219483700
tb.dut.u_reg.u_chk.PayLoadWidthCheck 001010101000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A 0016486829213735000
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A 0017471222717355921600
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A 001648682922400800
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 00174712227117400
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 001648682922518200
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 001747122272400600
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 001747122272400800
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682922400800
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 0016486829217234700
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A 0017471222717355921600
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 001648682923055300
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001648682923055100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 001747122273055900
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 001747122273055700
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682923058600
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0017471222717355921600
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 001648682924100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 001747122274100
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0017471222717355921600
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 001648682923800
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 001747122273800
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A 0016486829222494100
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A 00873554868677908200
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A 001648682922400800
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0087355486117400
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 001648682922518200
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 00873554862396700
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 00873554862400800
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682922400800
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 0016486829228110400
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A 00873554868677908200
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 001648682923043500
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001648682923043300
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00873554863044100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 00873554863043500
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682923047000
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 00873554868677908200
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 001648682923100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 00873554863100
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 00873554868677908200
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 001648682923600
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 00873554863600
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A 001648682929353100
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A 0035121887434661312900
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A 001648682922400800
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 00351218874117400
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 001648682922518200
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 003512188742400800
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 003512188742400800
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682922400800
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 0016486829211737000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A 0035121887434661312900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 001648682923044400
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001648682923044300
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 003512188743046200
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 003512188743045900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682923047300
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0035121887434661312900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 001648682923900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 003512188743900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0035121887434661312900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 001648682923900
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 003512188743900
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A 001648682929194900
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A 0037577560037093622300
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A 001648682922400800
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 00375775600117400
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 001648682922518200
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 003757756002400800
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 003757756002400800
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682922400800
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 0016486829211483800
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A 0037577560037093622300
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 001648682923041500
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001648682923041400
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 003757756003042900
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 003757756003042300
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682923044100
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0037577560037093622300
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 001648682922500
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 003757756002500
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0037577560037093622300
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 001648682922900
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 003757756002900
tb.dut.u_reg.u_reg_if.AllowedLatency_A 001010101000
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 001010101000
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 001010101000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001010101000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001010101000
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 001010101000
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 001010101000
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A 0016486829213475500
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A 0018035647817803439000
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A 001648682922351200
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 00180356478117400
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 001648682922468600
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 001803564782340200
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A 001803564782355400
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682922400800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A 0016486829217184500
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A 0018035647817803439000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A 001648682923041800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A 0016486829216212680500
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001648682923039700
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 001803564783053900
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A 001803564783050800
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M 001648682923070200
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A 0018035647817803439000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A 001648682924500
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M 001803564784500
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A 001010101000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A 0018035647817803439000
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A 001648682923400
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M 001803564783400
tb.dut.u_reg.wePulse 0016486829262438200
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A 0016392537116127809500
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq 00163925371260300
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq 00178931655260300
tb.dut.u_usb_meas.u_meas.RefCntVal_A 0080580500
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq 00178931655279134100
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A 0080580500
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A 0017893165510559600
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M 001245312510496200
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0080580500
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A 0017893165517781806900
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A 0017893165517781806900

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A 0016392537119338905058
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A 0016392537116105841102415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A 0037280715036815731502415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A 0034836926734394519002415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00174712227001010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0087355486001010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00351218874001010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00375775600001010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 00180356478001010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A 0016392537116127065902415


Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00164868923000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00164868923000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00164868923000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00164868923000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00164868923000
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00164868923000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00164868923902590250
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00164868923223822380
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00164868923932093200
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00164868923100355100355758

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00164868923902590250
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00164868923223822380
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00164868923932093200
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00164868923100355100355758

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