Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 346603076 1 T7 4330 T8 4028 T9 2458
auto[1] 480136 1 T9 266 T25 82 T27 544


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 346637828 1 T7 4330 T8 4028 T9 2524
auto[1] 445384 1 T9 200 T25 78 T4 3516


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 346551020 1 T7 4330 T8 4028 T9 2518
auto[1] 532192 1 T9 206 T25 78 T4 3516


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 317333062 1 T7 4330 T8 4028 T9 2724
auto[1] 29750150 1 T27 840 T6 2260 T1 27948


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 223262174 1 T7 700 T8 4008 T9 2724
auto[1] 123821038 1 T7 3630 T8 20 T24 1532


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 198359418 1 T7 700 T8 4008 T9 2402
auto[0] auto[0] auto[0] auto[0] auto[1] 118621276 1 T7 3630 T8 20 T24 1532
auto[0] auto[0] auto[0] auto[1] auto[0] 35838 1 T9 22 T25 20 T28 12
auto[0] auto[0] auto[0] auto[1] auto[1] 9060 1 T6 32 T1 124 T18 8
auto[0] auto[0] auto[1] auto[0] auto[0] 24247638 1 T27 402 T6 1094 T1 17634
auto[0] auto[0] auto[1] auto[0] auto[1] 5067950 1 T27 104 T6 174 T1 3494
auto[0] auto[0] auto[1] auto[1] auto[0] 63200 1 T27 64 T6 96 T1 1200
auto[0] auto[0] auto[1] auto[1] auto[1] 15548 1 T27 6 T6 12 T1 50
auto[0] auto[1] auto[0] auto[0] auto[0] 66220 1 T9 12 T6 2 T1 50
auto[0] auto[1] auto[0] auto[0] auto[1] 998 1 T1 8 T161 22 T15 32
auto[0] auto[1] auto[0] auto[1] auto[0] 13588 1 T9 82 T6 86 T1 100
auto[0] auto[1] auto[0] auto[1] auto[1] 2902 1 T1 46 T161 70 T15 158
auto[0] auto[1] auto[1] auto[0] auto[0] 14274 1 T27 2 T6 30 T1 72
auto[0] auto[1] auto[1] auto[0] auto[1] 3632 1 T6 20 T1 4 T18 28
auto[0] auto[1] auto[1] auto[1] auto[0] 24002 1 T27 54 T6 200 T1 388
auto[0] auto[1] auto[1] auto[1] auto[1] 5476 1 T6 60 T1 44 T18 62
auto[1] auto[0] auto[0] auto[0] auto[0] 44628 1 T9 22 T6 26 T1 188
auto[1] auto[0] auto[0] auto[0] auto[1] 4268 1 T6 22 T1 44 T18 10
auto[1] auto[0] auto[0] auto[1] auto[0] 35886 1 T9 78 T6 178 T1 422
auto[1] auto[0] auto[0] auto[1] auto[1] 8518 1 T6 58 T1 50 T18 86
auto[1] auto[0] auto[1] auto[0] auto[0] 36928 1 T27 4 T6 58 T1 436
auto[1] auto[0] auto[1] auto[0] auto[1] 8650 1 T27 2 T1 144 T21 12
auto[1] auto[0] auto[1] auto[1] auto[0] 62406 1 T27 96 T6 290 T1 1208
auto[1] auto[0] auto[1] auto[1] auto[1] 16616 1 T27 56 T1 110 T21 64
auto[1] auto[1] auto[0] auto[0] auto[0] 55406 1 T9 22 T25 16 T4 3516
auto[1] auto[1] auto[0] auto[0] auto[1] 6888 1 T27 12 T1 14 T21 34
auto[1] auto[1] auto[0] auto[1] auto[0] 54260 1 T9 84 T25 62 T27 220
auto[1] auto[1] auto[0] auto[1] auto[1] 13908 1 T1 60 T21 84 T135 180
auto[1] auto[1] auto[1] auto[0] auto[0] 52244 1 T27 2 T6 50 T1 544
auto[1] auto[1] auto[1] auto[0] auto[1] 12658 1 T6 50 T1 228 T18 44
auto[1] auto[1] auto[1] auto[1] auto[0] 96238 1 T27 48 T6 126 T1 1954
auto[1] auto[1] auto[1] auto[1] auto[1] 22690 1 T1 438 T99 82 T86 48

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