Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319160252 1 T4 2220 T1 624628 T5 2450
auto[1] 415322 1 T4 196 T1 8788 T2 6538


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319148512 1 T4 2244 T1 624894 T5 2450
auto[1] 427062 1 T4 172 T1 6136 T2 6020


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319072916 1 T4 2314 T1 624705 T5 2450
auto[1] 502658 1 T4 102 T1 8026 T2 6702


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304015194 1 T4 172 T1 622549 T5 2450
auto[1] 15560380 1 T4 2244 T1 29584 T2 19992


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 171999628 1 T4 2284 T1 812686 T5 2450
auto[1] 147575946 1 T4 132 T1 544239 T16 2774


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 162741676 1 T4 102 T1 787724 T5 2450
auto[0] auto[0] auto[0] auto[0] auto[1] 140902354 1 T1 543401 T16 2774 T2 340415
auto[0] auto[0] auto[0] auto[1] auto[0] 30570 1 T1 318 T2 476 T3 10
auto[0] auto[0] auto[0] auto[1] auto[1] 6548 1 T1 60 T2 54 T3 48
auto[0] auto[0] auto[1] auto[0] auto[0] 8634862 1 T4 2010 T1 17134 T2 9578
auto[0] auto[0] auto[1] auto[0] auto[1] 6554380 1 T4 58 T1 5464 T2 4622
auto[0] auto[0] auto[1] auto[1] auto[0] 52268 1 T1 700 T2 824 T3 30
auto[0] auto[0] auto[1] auto[1] auto[1] 13806 1 T4 74 T1 490 T2 296
auto[0] auto[1] auto[0] auto[0] auto[0] 81232 1 T4 8 T1 70 T2 262
auto[0] auto[1] auto[0] auto[0] auto[1] 1210 1 T1 26 T69 10 T14 2
auto[0] auto[1] auto[0] auto[1] auto[0] 11538 1 T4 62 T1 148 T2 216
auto[0] auto[1] auto[0] auto[1] auto[1] 2590 1 T1 92 T69 62 T14 42
auto[0] auto[1] auto[1] auto[0] auto[0] 11662 1 T1 74 T2 302 T3 12
auto[0] auto[1] auto[1] auto[0] auto[1] 2452 1 T1 46 T2 48 T11 10
auto[0] auto[1] auto[1] auto[1] auto[0] 21106 1 T1 420 T2 360 T3 52
auto[0] auto[1] auto[1] auto[1] auto[1] 4662 1 T1 274 T2 116 T68 54
auto[1] auto[0] auto[0] auto[0] auto[0] 58464 1 T1 226 T2 182 T3 50
auto[1] auto[0] auto[0] auto[0] auto[1] 4440 1 T1 24 T2 54 T113 10
auto[1] auto[0] auto[0] auto[1] auto[0] 32300 1 T1 1028 T2 374 T3 168
auto[1] auto[0] auto[0] auto[1] auto[1] 8902 1 T1 102 T114 78 T14 92
auto[1] auto[0] auto[1] auto[0] auto[0] 30262 1 T1 384 T2 396 T3 24
auto[1] auto[0] auto[1] auto[0] auto[1] 8124 1 T1 62 T2 80 T3 18
auto[1] auto[0] auto[1] auto[1] auto[0] 54592 1 T1 942 T2 628 T3 182
auto[1] auto[0] auto[1] auto[1] auto[1] 14964 1 T1 272 T2 272 T3 60
auto[1] auto[1] auto[0] auto[0] auto[0] 66932 1 T1 302 T2 774 T3 46
auto[1] auto[1] auto[0] auto[0] auto[1] 6880 1 T1 62 T2 178 T3 8
auto[1] auto[1] auto[0] auto[1] auto[0] 46962 1 T1 804 T2 970 T3 110
auto[1] auto[1] auto[0] auto[1] auto[1] 12596 1 T1 496 T2 324 T11 108
auto[1] auto[1] auto[1] auto[0] auto[0] 43302 1 T4 42 T1 470 T2 662
auto[1] auto[1] auto[1] auto[0] auto[1] 12020 1 T1 210 T2 180 T3 40
auto[1] auto[1] auto[1] auto[1] auto[0] 81900 1 T4 60 T1 1942 T2 1158
auto[1] auto[1] auto[1] auto[1] auto[1] 20018 1 T1 700 T2 470 T3 100

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