Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	580448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3223019

1

T5

24

T6

26

T1

90

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	935078	1			T5	42		T6	29		T1	26
values[0x0]	1319836	1			T5	17		T6	15		T1	72
values[0x1]	1548553	1			T5	22		T6	16		T1	98

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	324878	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3478589

1

T5

30

T6

32

T1

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14368	1			T1	1		T14	3		T2	1
valid_sources[0x01]	15493	1			T2	2		T7	289		T8	184
valid_sources[0x02]	14244	1			T1	1		T4	1		T7	267
valid_sources[0x03]	15061	1			T1	1		T2	2		T7	274
valid_sources[0x04]	16383	1			T5	1		T4	2		T7	284
valid_sources[0x05]	13819	1			T2	2		T4	1		T16	1
valid_sources[0x06]	14124	1			T4	1		T7	253		T8	167
valid_sources[0x07]	15388	1			T1	2		T2	1		T4	2
valid_sources[0x08]	17190	1			T5	2		T14	1		T16	1
valid_sources[0x09]	15548	1			T1	3		T2	1		T7	294
valid_sources[0x0a]	14419	1			T1	1		T7	283		T18	2
valid_sources[0x0b]	13483	1			T16	1		T7	312		T24	3
valid_sources[0x0c]	14788	1			T1	1		T2	1		T4	2
valid_sources[0x0d]	13927	1			T5	1		T1	1		T4	1
valid_sources[0x0e]	15586	1			T1	1		T7	286		T8	171
valid_sources[0x0f]	14961	1			T7	329		T24	2		T8	141
valid_sources[0x10]	14699	1			T5	1		T2	4		T7	276
valid_sources[0x11]	14213	1			T14	3		T2	1		T7	258
valid_sources[0x12]	13646	1			T5	2		T2	1		T4	1
valid_sources[0x13]	15038	1			T5	2		T1	2		T7	213
valid_sources[0x14]	14707	1			T5	2		T1	4		T16	1
valid_sources[0x15]	14465	1			T7	255		T8	137		T19	1
valid_sources[0x16]	14742	1			T1	1		T2	1		T7	232
valid_sources[0x17]	13294	1			T7	238		T8	162		T19	6
valid_sources[0x18]	15213	1			T4	1		T7	236		T8	166
valid_sources[0x19]	14123	1			T1	1		T2	1		T7	313
valid_sources[0x1a]	14744	1			T7	251		T36	2		T8	146
valid_sources[0x1b]	14729	1			T1	1		T2	1		T16	2
valid_sources[0x1c]	17418	1			T1	1		T2	2		T4	1
valid_sources[0x1d]	13897	1			T1	1		T7	247		T8	154
valid_sources[0x1e]	14655	1			T2	2		T16	1		T7	241
valid_sources[0x1f]	14249	1			T5	1		T2	1		T7	307
valid_sources[0x20]	13231	1			T7	279		T8	177		T19	1
valid_sources[0x21]	15009	1			T1	2		T7	268		T24	1
valid_sources[0x22]	14773	1			T1	1		T2	2		T4	1
valid_sources[0x23]	15082	1			T2	3		T7	255		T18	1
valid_sources[0x24]	15577	1			T1	2		T2	1		T4	1
valid_sources[0x25]	13661	1			T2	1		T4	1		T7	253
valid_sources[0x26]	13704	1			T5	2		T14	4		T2	1
valid_sources[0x27]	17208	1			T1	1		T4	4		T7	288
valid_sources[0x28]	14603	1			T2	1		T16	2		T7	296
valid_sources[0x29]	14061	1			T1	4		T16	1		T7	285
valid_sources[0x2a]	15055	1			T2	1		T7	282		T8	183
valid_sources[0x2b]	15445	1			T1	1		T2	1		T7	254
valid_sources[0x2c]	15940	1			T5	1		T1	1		T7	292
valid_sources[0x2d]	15031	1			T14	1		T7	250		T24	1
valid_sources[0x2e]	14007	1			T7	305		T8	159		T37	2
valid_sources[0x2f]	15003	1			T1	2		T2	1		T4	1
valid_sources[0x30]	14819	1			T14	2		T2	2		T7	305
valid_sources[0x31]	15999	1			T2	4		T4	3		T7	274
valid_sources[0x32]	14923	1			T2	1		T16	1		T7	242
valid_sources[0x33]	14081	1			T5	1		T1	2		T7	225
valid_sources[0x34]	15633	1			T14	1		T2	2		T4	2
valid_sources[0x35]	15678	1			T5	2		T1	1		T2	2
valid_sources[0x36]	14373	1			T14	6		T2	2		T7	257
valid_sources[0x37]	14701	1			T14	3		T2	3		T4	1
valid_sources[0x38]	13690	1			T1	1		T2	1		T7	246
valid_sources[0x39]	15306	1			T5	3		T2	3		T4	1
valid_sources[0x3a]	14390	1			T7	274		T8	120		T19	3
valid_sources[0x3b]	14639	1			T1	1		T2	1		T7	269
valid_sources[0x3c]	15166	1			T2	1		T7	294		T8	190
valid_sources[0x3d]	14838	1			T1	1		T14	1		T4	1
valid_sources[0x3e]	15240	1			T5	1		T7	250		T8	140
valid_sources[0x3f]	14521	1			T7	235		T8	183		T55	1
valid_sources[0x40]	13449	1			T1	2		T2	2		T4	1
valid_sources[0x41]	14040	1			T2	2		T4	2		T7	316
valid_sources[0x42]	15748	1			T1	2		T2	1		T7	257
valid_sources[0x43]	14502	1			T1	1		T14	4		T4	5
valid_sources[0x44]	14668	1			T1	1		T14	2		T2	1
valid_sources[0x45]	13657	1			T1	2		T2	1		T7	243
valid_sources[0x46]	13723	1			T7	275		T8	175		T21	4
valid_sources[0x47]	14107	1			T2	1		T16	1		T7	264
valid_sources[0x48]	14431	1			T2	2		T7	264		T8	144
valid_sources[0x49]	15088	1			T6	18		T1	2		T4	1
valid_sources[0x4a]	14837	1			T5	1		T1	2		T14	4
valid_sources[0x4b]	17175	1			T3	1519		T7	264		T18	1
valid_sources[0x4c]	15939	1			T1	1		T2	5		T7	284
valid_sources[0x4d]	14750	1			T7	314		T24	3		T8	174
valid_sources[0x4e]	14260	1			T1	1		T16	1		T7	257
valid_sources[0x4f]	16895	1			T1	1		T2	7		T7	294
valid_sources[0x50]	16795	1			T14	2		T2	3		T4	2
valid_sources[0x51]	14058	1			T1	1		T2	2		T4	2
valid_sources[0x52]	13519	1			T2	2		T7	305		T24	1
valid_sources[0x53]	15321	1			T2	2		T4	2		T7	280
valid_sources[0x54]	16781	1			T4	2		T7	288		T24	1
valid_sources[0x55]	15397	1			T7	290		T24	1		T8	172
valid_sources[0x56]	13982	1			T5	2		T1	1		T7	299
valid_sources[0x57]	14508	1			T14	3		T2	2		T4	1
valid_sources[0x58]	14987	1			T14	3		T2	2		T16	1
valid_sources[0x59]	15428	1			T1	1		T2	2		T7	287
valid_sources[0x5a]	14561	1			T1	2		T2	1		T7	298
valid_sources[0x5b]	14981	1			T1	1		T7	284		T24	1
valid_sources[0x5c]	14735	1			T1	2		T2	1		T7	276
valid_sources[0x5d]	15542	1			T16	2		T7	230		T24	2
valid_sources[0x5e]	15704	1			T7	258		T24	1		T8	145
valid_sources[0x5f]	14397	1			T1	2		T7	255		T8	220
valid_sources[0x60]	15942	1			T1	1		T2	1		T7	247
valid_sources[0x61]	14546	1			T5	1		T14	3		T2	1
valid_sources[0x62]	15037	1			T2	1		T4	2		T7	285
valid_sources[0x63]	15492	1			T1	1		T14	1		T16	1
valid_sources[0x64]	16308	1			T1	2		T2	1		T4	1
valid_sources[0x65]	16320	1			T1	1		T2	1		T4	7
valid_sources[0x66]	15084	1			T5	1		T1	1		T4	1
valid_sources[0x67]	13989	1			T2	1		T7	269		T8	169
valid_sources[0x68]	15215	1			T5	2		T1	1		T4	2
valid_sources[0x69]	15287	1			T1	2		T2	3		T7	304
valid_sources[0x6a]	15530	1			T5	2		T1	1		T2	1
valid_sources[0x6b]	14993	1			T4	3		T7	249		T18	2
valid_sources[0x6c]	15237	1			T5	2		T1	2		T14	3
valid_sources[0x6d]	15302	1			T14	1		T2	1		T7	266
valid_sources[0x6e]	14996	1			T1	1		T2	2		T16	1
valid_sources[0x6f]	15109	1			T5	6		T4	1		T7	279
valid_sources[0x70]	13921	1			T1	1		T4	1		T7	265
valid_sources[0x71]	14023	1			T16	1		T7	261		T24	3
valid_sources[0x72]	15298	1			T5	1		T1	1		T4	2
valid_sources[0x73]	14870	1			T5	2		T7	276		T8	179
valid_sources[0x74]	15176	1			T5	2		T7	254		T8	143
valid_sources[0x75]	14672	1			T1	1		T2	2		T7	292
valid_sources[0x76]	13621	1			T2	2		T16	1		T7	256
valid_sources[0x77]	14349	1			T7	265		T8	145		T19	5
valid_sources[0x78]	15023	1			T4	1		T7	288		T18	1
valid_sources[0x79]	14389	1			T2	1		T7	260		T8	182
valid_sources[0x7a]	14221	1			T7	242		T8	172		T57	2
valid_sources[0x7b]	14632	1			T1	2		T4	1		T7	285
valid_sources[0x7c]	15378	1			T14	1		T4	4		T7	324
valid_sources[0x7d]	15386	1			T1	1		T4	1		T7	266
valid_sources[0x7e]	16263	1			T2	1		T16	1		T7	282
valid_sources[0x7f]	14505	1			T1	1		T4	1		T7	264
valid_sources[0x80]	17753	1			T5	1		T1	2		T7	304

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

813943

1

T5

17

T6

16

T1

14

values[0x0]

all_enables

biggest_size

1227766

1

T5

4

T6

6

T1

41

values[0x1]

all_enables

biggest_size

1181310

1

T5

3

T6

4

T1

35