Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
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Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
PeriDiv2 100.00 1 100 1 64 64
PeriDiv4 100.00 1 100 1 64 64
PeriIo 100.00 1 100 1 64 64
PeriUsb 100.00 1 100 1 64 64




Group Instance : PeriDiv2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv2
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriDiv4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriIo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriIo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriIo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriIo
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriUsb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriUsb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriUsb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriUsb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 358348 1 T5 8 T6 2 T1 2
auto[1] 227794032 1 T5 938 T6 1121 T1 44928



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8793 1 T5 2 T6 2 T1 2
auto[1] 228143587 1 T5 944 T6 1121 T1 44928



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118926009 1 T5 941 T6 1064 T1 44930
auto[1] 109226371 1 T5 5 T6 59 T14 48



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5250 1 T1 2 T14 200 T15 2
auto[0] auto[0] auto[1] 1602 1 T5 2 T6 2 T14 2
auto[0] auto[1] auto[0] 275430 1 T5 6 T3 138 T7 167
auto[0] auto[1] auto[1] 76066 1 T3 274 T7 213 T8 2410
auto[1] auto[1] auto[0] 118643388 1 T5 935 T6 1064 T1 44928
auto[1] auto[1] auto[1] 109148703 1 T5 3 T6 57 T14 46


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160056 1 T5 5 T6 2 T1 2
auto[1] 113914235 1 T5 468 T6 556 T1 22464



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7828 1 T5 2 T6 2 T1 2
auto[1] 114066463 1 T5 471 T6 556 T1 22464



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 59461053 1 T5 471 T6 528 T1 22466
auto[1] 54613238 1 T5 2 T6 30 T14 25



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5250 1 T1 2 T14 200 T15 2
auto[0] auto[0] auto[1] 1602 1 T5 2 T6 2 T14 2
auto[0] auto[1] auto[0] 114773 1 T5 3 T3 91 T7 80
auto[0] auto[1] auto[1] 38431 1 T3 105 T7 104 T8 1392
auto[1] auto[1] auto[0] 59340054 1 T5 468 T6 528 T1 22464
auto[1] auto[1] auto[1] 54573205 1 T6 28 T14 23 T2 7


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 656959 1 T5 14 T6 2 T1 2
auto[1] 454984455 1 T5 1878 T6 1929 T1 89859



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10732 1 T5 2 T6 2 T1 2
auto[1] 455630682 1 T5 1890 T6 1929 T1 89859



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 237188740 1 T5 1882 T6 1811 T1 89861
auto[1] 218452674 1 T5 10 T6 120 T14 97



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5250 1 T1 2 T14 200 T15 2
auto[0] auto[0] auto[1] 1602 1 T5 2 T6 2 T14 2
auto[0] auto[1] auto[0] 502579 1 T5 12 T3 410 T7 354
auto[0] auto[1] auto[1] 147528 1 T3 410 T7 406 T8 5292
auto[1] auto[1] auto[0] 236677031 1 T5 1870 T6 1811 T1 89859
auto[1] auto[1] auto[1] 218303544 1 T5 8 T6 118 T14 95


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 365911 1 T5 8 T6 2 T1 2
auto[1] 232726985 1 T5 939 T6 963 T1 44931



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8371 1 T5 2 T6 2 T1 2
auto[1] 233084525 1 T5 945 T6 963 T1 44931



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121745665 1 T5 941 T6 905 T1 44933
auto[1] 111347231 1 T5 6 T6 60 T14 48



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5246 1 T1 2 T14 200 T15 2
auto[0] auto[0] auto[1] 1606 1 T5 2 T6 2 T14 2
auto[0] auto[1] auto[0] 283560 1 T5 6 T3 138 T7 158
auto[0] auto[1] auto[1] 75499 1 T3 238 T7 223 T8 2696
auto[1] auto[1] auto[0] 121455340 1 T5 935 T6 905 T1 44931
auto[1] auto[1] auto[1] 111270126 1 T5 4 T6 58 T14 46


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded

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