Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T16
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T23,T32,T33
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1032329899	13358	0	0
GateOpen_A	1032329899	19839	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032329899	13358	0	0
T1	202529	0	0	0
T2	265546	0	0	0
T3	1040577	43	0	0
T4	197999	0	0	0
T5	4627	4	0	0
T6	4837	0	0	0
T7	0	145	0	0
T8	0	64	0	0
T9	0	8	0	0
T14	252814	0	0	0
T15	23172	0	0	0
T16	29985	0	0	0
T17	4306	0	0	0
T23	0	17	0	0
T32	0	13	0	0
T33	0	15	0	0
T54	0	21	0	0
T55	0	23	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032329899	19839	0	0
T1	202529	4	0	0
T2	265546	0	0	0
T3	1040577	47	0	0
T4	197999	0	0	0
T5	4627	4	0	0
T6	4837	0	0	0
T7	0	161	0	0
T14	252814	400	0	0
T15	23172	4	0	0
T16	29985	204	0	0
T17	4306	0	0	0
T18	0	4	0	0
T23	0	21	0	0
T24	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T16
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T23,T32,T33
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	113880084	3220	0	0
GateOpen_A	113880084	4837	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113880084	3220	0	0
T1	22483	0	0	0
T2	29496	0	0	0
T3	113743	10	0	0
T4	21991	0	0	0
T5	501	1	0	0
T6	566	0	0	0
T7	0	32	0	0
T8	0	14	0	0
T9	0	2	0	0
T14	26641	0	0	0
T15	2744	0	0	0
T16	2659	0	0	0
T17	468	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	4	0	0
T55	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113880084	4837	0	0
T1	22483	1	0	0
T2	29496	0	0	0
T3	113743	11	0	0
T4	21991	0	0	0
T5	501	1	0	0
T6	566	0	0	0
T7	0	36	0	0
T14	26641	100	0	0
T15	2744	1	0	0
T16	2659	51	0	0
T17	468	0	0	0
T18	0	1	0	0
T23	0	5	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T16
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T23,T32,T33
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	227761071	3397	0	0
GateOpen_A	227761071	5014	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227761071	3397	0	0
T1	44966	0	0	0
T2	58992	0	0	0
T3	227488	12	0	0
T4	43982	0	0	0
T5	1002	1	0	0
T6	1132	0	0	0
T7	0	38	0	0
T8	0	16	0	0
T9	0	2	0	0
T14	53285	0	0	0
T15	5489	0	0	0
T16	5315	0	0	0
T17	935	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	5	0	0
T55	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227761071	5014	0	0
T1	44966	1	0	0
T2	58992	0	0	0
T3	227488	13	0	0
T4	43982	0	0	0
T5	1002	1	0	0
T6	1132	0	0	0
T7	0	42	0	0
T14	53285	100	0	0
T15	5489	1	0	0
T16	5315	51	0	0
T17	935	0	0	0
T18	0	1	0	0
T23	0	5	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T16
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T23,T32,T33
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	456926151	3385	0	0
GateOpen_A	456926151	5008	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926151	3385	0	0
T1	90052	0	0	0
T2	118037	0	0	0
T3	454703	11	0	0
T4	88016	0	0	0
T5	2083	1	0	0
T6	2093	0	0	0
T7	0	37	0	0
T8	0	17	0	0
T9	0	2	0	0
T14	115257	0	0	0
T15	9959	0	0	0
T16	14674	0	0	0
T17	1935	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	5	0	0
T55	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456926151	5008	0	0
T1	90052	1	0	0
T2	118037	0	0	0
T3	454703	12	0	0
T4	88016	0	0	0
T5	2083	1	0	0
T6	2093	0	0	0
T7	0	41	0	0
T14	115257	100	0	0
T15	9959	1	0	0
T16	14674	51	0	0
T17	1935	0	0	0
T18	0	1	0	0
T23	0	5	0	0
T24	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T16
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T23,T32,T33
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233762593	3356	0	0
GateOpen_A	233762593	4980	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762593	3356	0	0
T1	45028	0	0	0
T2	59021	0	0	0
T3	244643	10	0	0
T4	44010	0	0	0
T5	1041	1	0	0
T6	1046	0	0	0
T7	0	38	0	0
T8	0	17	0	0
T9	0	2	0	0
T14	57631	0	0	0
T15	4980	0	0	0
T16	7337	0	0	0
T17	968	0	0	0
T23	0	5	0	0
T32	0	4	0	0
T33	0	3	0	0
T54	0	7	0	0
T55	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762593	4980	0	0
T1	45028	1	0	0
T2	59021	0	0	0
T3	244643	11	0	0
T4	44010	0	0	0
T5	1041	1	0	0
T6	1046	0	0	0
T7	0	42	0	0
T14	57631	100	0	0
T15	4980	1	0	0
T16	7337	51	0	0
T17	968	0	0	0
T18	0	1	0	0
T23	0	6	0	0
T24	0	1	0	0