Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	759854630	68320	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759854630	68320	0	0
T1	117255	83	0	0
T2	153695	96	0	0
T3	647585	90	0	0
T4	458425	0	0	0
T7	1005700	786	0	0
T8	0	149	0	0
T9	0	91	0	0
T10	0	939	0	0
T11	0	303	0	0
T12	0	121	0	0
T13	0	670	0	0
T14	90040	0	0	0
T15	7255	0	0	0
T16	73365	0	0	0
T17	5235	0	0	0
T18	10730	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151970926	10028	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	10028	0	0
T1	23451	13	0	0
T2	30739	15	0	0
T3	129517	14	0	0
T4	91685	0	0	0
T7	201140	116	0	0
T8	0	27	0	0
T9	0	12	0	0
T10	0	122	0	0
T11	0	55	0	0
T12	0	20	0	0
T13	0	98	0	0
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151970926	10021	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	10021	0	0
T1	23451	13	0	0
T2	30739	15	0	0
T3	129517	14	0	0
T4	91685	0	0	0
T7	201140	99	0	0
T8	0	27	0	0
T9	0	12	0	0
T10	0	124	0	0
T11	0	55	0	0
T12	0	18	0	0
T13	0	96	0	0
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151970926	13801	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	13801	0	0
T1	23451	17	0	0
T2	30739	19	0	0
T3	129517	18	0	0
T4	91685	0	0	0
T7	201140	154	0	0
T8	0	29	0	0
T9	0	18	0	0
T10	0	192	0	0
T11	0	59	0	0
T12	0	24	0	0
T13	0	135	0	0
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151970926	13709	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	13709	0	0
T1	23451	17	0	0
T2	30739	19	0	0
T3	129517	18	0	0
T4	91685	0	0	0
T7	201140	161	0	0
T8	0	29	0	0
T9	0	19	0	0
T10	0	188	0	0
T11	0	59	0	0
T12	0	25	0	0
T13	0	133	0	0
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151970926	20761	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	20761	0	0
T1	23451	23	0	0
T2	30739	28	0	0
T3	129517	26	0	0
T4	91685	0	0	0
T7	201140	256	0	0
T8	0	37	0	0
T9	0	30	0	0
T10	0	313	0	0
T11	0	75	0	0
T12	0	34	0	0
T13	0	208	0	0
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0