Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T3 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T14 |
28 |
28 |
0 |
0 |
T15 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1465145 |
1462386 |
0 |
0 |
T2 |
1920557 |
1918321 |
0 |
0 |
T3 |
7949493 |
7931922 |
0 |
0 |
T4 |
2394766 |
2390752 |
0 |
0 |
T5 |
55385 |
50748 |
0 |
0 |
T6 |
56466 |
52286 |
0 |
0 |
T14 |
1700736 |
1483435 |
0 |
0 |
T15 |
146799 |
145298 |
0 |
0 |
T16 |
387651 |
187066 |
0 |
0 |
T17 |
39041 |
35448 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
911825556 |
900472932 |
0 |
14490 |
T1 |
140706 |
140394 |
0 |
18 |
T2 |
184434 |
184164 |
0 |
18 |
T3 |
777102 |
775098 |
0 |
18 |
T4 |
550110 |
549078 |
0 |
18 |
T5 |
12492 |
11334 |
0 |
18 |
T6 |
12822 |
11808 |
0 |
18 |
T14 |
108048 |
90618 |
0 |
18 |
T15 |
8706 |
8586 |
0 |
18 |
T16 |
88038 |
38274 |
0 |
18 |
T17 |
6282 |
5610 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
512177 |
511080 |
0 |
21 |
T2 |
671350 |
670407 |
0 |
21 |
T3 |
2776393 |
2769090 |
0 |
21 |
T4 |
638125 |
636928 |
0 |
21 |
T5 |
14926 |
13543 |
0 |
21 |
T6 |
15087 |
13896 |
0 |
21 |
T14 |
631520 |
536356 |
0 |
21 |
T15 |
54352 |
53672 |
0 |
21 |
T16 |
105163 |
45629 |
0 |
21 |
T17 |
12093 |
10803 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
193458 |
0 |
0 |
T1 |
512177 |
4 |
0 |
0 |
T2 |
671350 |
4 |
0 |
0 |
T3 |
2776393 |
498 |
0 |
0 |
T4 |
638125 |
4 |
0 |
0 |
T5 |
8680 |
16 |
0 |
0 |
T6 |
15087 |
190 |
0 |
0 |
T7 |
593628 |
707 |
0 |
0 |
T9 |
0 |
48 |
0 |
0 |
T14 |
631520 |
12 |
0 |
0 |
T15 |
54352 |
129 |
0 |
0 |
T16 |
105163 |
12 |
0 |
0 |
T17 |
12093 |
9 |
0 |
0 |
T18 |
0 |
49 |
0 |
0 |
T36 |
0 |
69 |
0 |
0 |
T58 |
0 |
78 |
0 |
0 |
T59 |
0 |
84 |
0 |
0 |
T61 |
0 |
7 |
0 |
0 |
T94 |
0 |
79 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
812262 |
810873 |
0 |
0 |
T2 |
1064773 |
1063711 |
0 |
0 |
T3 |
4395998 |
4387422 |
0 |
0 |
T4 |
1206531 |
1204707 |
0 |
0 |
T5 |
27967 |
25832 |
0 |
0 |
T6 |
28557 |
26543 |
0 |
0 |
T14 |
961168 |
852522 |
0 |
0 |
T15 |
83741 |
83001 |
0 |
0 |
T16 |
194450 |
101174 |
0 |
0 |
T17 |
20666 |
18996 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456925693 |
452852000 |
0 |
0 |
T1 |
90051 |
89861 |
0 |
0 |
T2 |
118036 |
117874 |
0 |
0 |
T3 |
454703 |
453444 |
0 |
0 |
T4 |
88015 |
87853 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2093 |
1931 |
0 |
0 |
T14 |
115256 |
98253 |
0 |
0 |
T15 |
9958 |
9837 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1935 |
1732 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456925693 |
452845097 |
0 |
2415 |
T1 |
90051 |
89858 |
0 |
3 |
T2 |
118036 |
117871 |
0 |
3 |
T3 |
454703 |
453420 |
0 |
3 |
T4 |
88015 |
87850 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2093 |
1928 |
0 |
3 |
T14 |
115256 |
97950 |
0 |
3 |
T15 |
9958 |
9834 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1935 |
1729 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456925693 |
28222 |
0 |
0 |
T1 |
90051 |
0 |
0 |
0 |
T2 |
118036 |
0 |
0 |
0 |
T3 |
454703 |
35 |
0 |
0 |
T4 |
88015 |
0 |
0 |
0 |
T6 |
2093 |
43 |
0 |
0 |
T7 |
191348 |
303 |
0 |
0 |
T14 |
115256 |
0 |
0 |
0 |
T15 |
9958 |
35 |
0 |
0 |
T16 |
14673 |
0 |
0 |
0 |
T17 |
1935 |
2 |
0 |
0 |
T18 |
0 |
26 |
0 |
0 |
T36 |
0 |
30 |
0 |
0 |
T58 |
0 |
33 |
0 |
0 |
T59 |
0 |
37 |
0 |
0 |
T94 |
0 |
39 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T3 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T3 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T3 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T3 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T3 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
17482 |
0 |
0 |
T1 |
23451 |
0 |
0 |
0 |
T2 |
30739 |
0 |
0 |
0 |
T3 |
129517 |
21 |
0 |
0 |
T4 |
91685 |
0 |
0 |
0 |
T6 |
2137 |
49 |
0 |
0 |
T7 |
201140 |
192 |
0 |
0 |
T9 |
0 |
48 |
0 |
0 |
T14 |
18008 |
0 |
0 |
0 |
T15 |
1451 |
20 |
0 |
0 |
T16 |
14673 |
0 |
0 |
0 |
T17 |
1047 |
0 |
0 |
0 |
T36 |
0 |
13 |
0 |
0 |
T58 |
0 |
31 |
0 |
0 |
T59 |
0 |
29 |
0 |
0 |
T61 |
0 |
7 |
0 |
0 |
T94 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T6,T15,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T15,T17 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
20123 |
0 |
0 |
T1 |
23451 |
0 |
0 |
0 |
T2 |
30739 |
0 |
0 |
0 |
T3 |
129517 |
39 |
0 |
0 |
T4 |
91685 |
0 |
0 |
0 |
T6 |
2137 |
41 |
0 |
0 |
T7 |
201140 |
212 |
0 |
0 |
T14 |
18008 |
0 |
0 |
0 |
T15 |
1451 |
22 |
0 |
0 |
T16 |
14673 |
0 |
0 |
0 |
T17 |
1047 |
1 |
0 |
0 |
T18 |
0 |
23 |
0 |
0 |
T36 |
0 |
26 |
0 |
0 |
T58 |
0 |
14 |
0 |
0 |
T59 |
0 |
18 |
0 |
0 |
T94 |
0 |
37 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
484765821 |
0 |
0 |
T1 |
93806 |
93680 |
0 |
0 |
T2 |
122959 |
122904 |
0 |
0 |
T3 |
515664 |
515064 |
0 |
0 |
T4 |
91685 |
91630 |
0 |
0 |
T5 |
2170 |
2086 |
0 |
0 |
T6 |
2180 |
2040 |
0 |
0 |
T14 |
120062 |
110963 |
0 |
0 |
T15 |
10373 |
10318 |
0 |
0 |
T16 |
15286 |
11016 |
0 |
0 |
T17 |
2016 |
1947 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
484765821 |
0 |
0 |
T1 |
93806 |
93680 |
0 |
0 |
T2 |
122959 |
122904 |
0 |
0 |
T3 |
515664 |
515064 |
0 |
0 |
T4 |
91685 |
91630 |
0 |
0 |
T5 |
2170 |
2086 |
0 |
0 |
T6 |
2180 |
2040 |
0 |
0 |
T14 |
120062 |
110963 |
0 |
0 |
T15 |
10373 |
10318 |
0 |
0 |
T16 |
15286 |
11016 |
0 |
0 |
T17 |
2016 |
1947 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456925693 |
454862394 |
0 |
0 |
T1 |
90051 |
89930 |
0 |
0 |
T2 |
118036 |
117983 |
0 |
0 |
T3 |
454703 |
454130 |
0 |
0 |
T4 |
88015 |
87962 |
0 |
0 |
T5 |
2082 |
2002 |
0 |
0 |
T6 |
2093 |
1958 |
0 |
0 |
T14 |
115256 |
106520 |
0 |
0 |
T15 |
9958 |
9905 |
0 |
0 |
T16 |
14673 |
10601 |
0 |
0 |
T17 |
1935 |
1869 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456925693 |
454862394 |
0 |
0 |
T1 |
90051 |
89930 |
0 |
0 |
T2 |
118036 |
117983 |
0 |
0 |
T3 |
454703 |
454130 |
0 |
0 |
T4 |
88015 |
87962 |
0 |
0 |
T5 |
2082 |
2002 |
0 |
0 |
T6 |
2093 |
1958 |
0 |
0 |
T14 |
115256 |
106520 |
0 |
0 |
T15 |
9958 |
9905 |
0 |
0 |
T16 |
14673 |
10601 |
0 |
0 |
T17 |
1935 |
1869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227760658 |
227760658 |
0 |
0 |
T1 |
44965 |
44965 |
0 |
0 |
T2 |
58992 |
58992 |
0 |
0 |
T3 |
227488 |
227488 |
0 |
0 |
T4 |
43981 |
43981 |
0 |
0 |
T5 |
1001 |
1001 |
0 |
0 |
T6 |
1131 |
1131 |
0 |
0 |
T14 |
53284 |
53284 |
0 |
0 |
T15 |
5489 |
5489 |
0 |
0 |
T16 |
5314 |
5314 |
0 |
0 |
T17 |
935 |
935 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
227760658 |
227760658 |
0 |
0 |
T1 |
44965 |
44965 |
0 |
0 |
T2 |
58992 |
58992 |
0 |
0 |
T3 |
227488 |
227488 |
0 |
0 |
T4 |
43981 |
43981 |
0 |
0 |
T5 |
1001 |
1001 |
0 |
0 |
T6 |
1131 |
1131 |
0 |
0 |
T14 |
53284 |
53284 |
0 |
0 |
T15 |
5489 |
5489 |
0 |
0 |
T16 |
5314 |
5314 |
0 |
0 |
T17 |
935 |
935 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113879664 |
113879664 |
0 |
0 |
T1 |
22483 |
22483 |
0 |
0 |
T2 |
29496 |
29496 |
0 |
0 |
T3 |
113743 |
113743 |
0 |
0 |
T4 |
21991 |
21991 |
0 |
0 |
T5 |
501 |
501 |
0 |
0 |
T6 |
565 |
565 |
0 |
0 |
T14 |
26640 |
26640 |
0 |
0 |
T15 |
2744 |
2744 |
0 |
0 |
T16 |
2658 |
2658 |
0 |
0 |
T17 |
467 |
467 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113879664 |
113879664 |
0 |
0 |
T1 |
22483 |
22483 |
0 |
0 |
T2 |
29496 |
29496 |
0 |
0 |
T3 |
113743 |
113743 |
0 |
0 |
T4 |
21991 |
21991 |
0 |
0 |
T5 |
501 |
501 |
0 |
0 |
T6 |
565 |
565 |
0 |
0 |
T14 |
26640 |
26640 |
0 |
0 |
T15 |
2744 |
2744 |
0 |
0 |
T16 |
2658 |
2658 |
0 |
0 |
T17 |
467 |
467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233762166 |
232723188 |
0 |
0 |
T1 |
45027 |
44967 |
0 |
0 |
T2 |
59020 |
58994 |
0 |
0 |
T3 |
244642 |
244355 |
0 |
0 |
T4 |
44009 |
43983 |
0 |
0 |
T5 |
1041 |
1002 |
0 |
0 |
T6 |
1046 |
979 |
0 |
0 |
T14 |
57630 |
53267 |
0 |
0 |
T15 |
4979 |
4953 |
0 |
0 |
T16 |
7337 |
5289 |
0 |
0 |
T17 |
967 |
934 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233762166 |
232723188 |
0 |
0 |
T1 |
45027 |
44967 |
0 |
0 |
T2 |
59020 |
58994 |
0 |
0 |
T3 |
244642 |
244355 |
0 |
0 |
T4 |
44009 |
43983 |
0 |
0 |
T5 |
1041 |
1002 |
0 |
0 |
T6 |
1046 |
979 |
0 |
0 |
T14 |
57630 |
53267 |
0 |
0 |
T15 |
4979 |
4953 |
0 |
0 |
T16 |
7337 |
5289 |
0 |
0 |
T17 |
967 |
934 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150078822 |
0 |
2415 |
T1 |
23451 |
23399 |
0 |
3 |
T2 |
30739 |
30694 |
0 |
3 |
T3 |
129517 |
129183 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2082 |
1889 |
0 |
3 |
T6 |
2137 |
1968 |
0 |
3 |
T14 |
18008 |
15103 |
0 |
3 |
T15 |
1451 |
1431 |
0 |
3 |
T16 |
14673 |
6379 |
0 |
3 |
T17 |
1047 |
935 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151970926 |
150085882 |
0 |
0 |
T1 |
23451 |
23402 |
0 |
0 |
T2 |
30739 |
30697 |
0 |
0 |
T3 |
129517 |
129207 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2082 |
1892 |
0 |
0 |
T6 |
2137 |
1971 |
0 |
0 |
T14 |
18008 |
15406 |
0 |
0 |
T15 |
1451 |
1434 |
0 |
0 |
T16 |
14673 |
6532 |
0 |
0 |
T17 |
1047 |
938 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482631564 |
0 |
2415 |
T1 |
93806 |
93606 |
0 |
3 |
T2 |
122959 |
122787 |
0 |
3 |
T3 |
515664 |
514326 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2170 |
1969 |
0 |
3 |
T6 |
2180 |
2008 |
0 |
3 |
T14 |
120062 |
102050 |
0 |
3 |
T15 |
10373 |
10244 |
0 |
3 |
T16 |
15286 |
6623 |
0 |
3 |
T17 |
2016 |
1801 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
32103 |
0 |
0 |
T1 |
93806 |
1 |
0 |
0 |
T2 |
122959 |
1 |
0 |
0 |
T3 |
515664 |
98 |
0 |
0 |
T4 |
91685 |
1 |
0 |
0 |
T5 |
2170 |
4 |
0 |
0 |
T6 |
2180 |
9 |
0 |
0 |
T14 |
120062 |
3 |
0 |
0 |
T15 |
10373 |
13 |
0 |
0 |
T16 |
15286 |
3 |
0 |
0 |
T17 |
2016 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482631564 |
0 |
2415 |
T1 |
93806 |
93606 |
0 |
3 |
T2 |
122959 |
122787 |
0 |
3 |
T3 |
515664 |
514326 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2170 |
1969 |
0 |
3 |
T6 |
2180 |
2008 |
0 |
3 |
T14 |
120062 |
102050 |
0 |
3 |
T15 |
10373 |
10244 |
0 |
3 |
T16 |
15286 |
6623 |
0 |
3 |
T17 |
2016 |
1801 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
31755 |
0 |
0 |
T1 |
93806 |
1 |
0 |
0 |
T2 |
122959 |
1 |
0 |
0 |
T3 |
515664 |
92 |
0 |
0 |
T4 |
91685 |
1 |
0 |
0 |
T5 |
2170 |
4 |
0 |
0 |
T6 |
2180 |
16 |
0 |
0 |
T14 |
120062 |
3 |
0 |
0 |
T15 |
10373 |
11 |
0 |
0 |
T16 |
15286 |
3 |
0 |
0 |
T17 |
2016 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482631564 |
0 |
2415 |
T1 |
93806 |
93606 |
0 |
3 |
T2 |
122959 |
122787 |
0 |
3 |
T3 |
515664 |
514326 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2170 |
1969 |
0 |
3 |
T6 |
2180 |
2008 |
0 |
3 |
T14 |
120062 |
102050 |
0 |
3 |
T15 |
10373 |
10244 |
0 |
3 |
T16 |
15286 |
6623 |
0 |
3 |
T17 |
2016 |
1801 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
32082 |
0 |
0 |
T1 |
93806 |
1 |
0 |
0 |
T2 |
122959 |
1 |
0 |
0 |
T3 |
515664 |
112 |
0 |
0 |
T4 |
91685 |
1 |
0 |
0 |
T5 |
2170 |
4 |
0 |
0 |
T6 |
2180 |
16 |
0 |
0 |
T14 |
120062 |
3 |
0 |
0 |
T15 |
10373 |
14 |
0 |
0 |
T16 |
15286 |
3 |
0 |
0 |
T17 |
2016 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T1 |
1 | Covered | T5,T6,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T1 |
0 |
Covered |
T5,T6,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482631564 |
0 |
2415 |
T1 |
93806 |
93606 |
0 |
3 |
T2 |
122959 |
122787 |
0 |
3 |
T3 |
515664 |
514326 |
0 |
3 |
T4 |
91685 |
91513 |
0 |
3 |
T5 |
2170 |
1969 |
0 |
3 |
T6 |
2180 |
2008 |
0 |
3 |
T14 |
120062 |
102050 |
0 |
3 |
T15 |
10373 |
10244 |
0 |
3 |
T16 |
15286 |
6623 |
0 |
3 |
T17 |
2016 |
1801 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
31691 |
0 |
0 |
T1 |
93806 |
1 |
0 |
0 |
T2 |
122959 |
1 |
0 |
0 |
T3 |
515664 |
101 |
0 |
0 |
T4 |
91685 |
1 |
0 |
0 |
T5 |
2170 |
4 |
0 |
0 |
T6 |
2180 |
16 |
0 |
0 |
T14 |
120062 |
3 |
0 |
0 |
T15 |
10373 |
14 |
0 |
0 |
T16 |
15286 |
3 |
0 |
0 |
T17 |
2016 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486939026 |
482638496 |
0 |
0 |
T1 |
93806 |
93609 |
0 |
0 |
T2 |
122959 |
122790 |
0 |
0 |
T3 |
515664 |
514350 |
0 |
0 |
T4 |
91685 |
91516 |
0 |
0 |
T5 |
2170 |
1972 |
0 |
0 |
T6 |
2180 |
2011 |
0 |
0 |
T14 |
120062 |
102353 |
0 |
0 |
T15 |
10373 |
10247 |
0 |
0 |
T16 |
15286 |
6776 |
0 |
0 |
T17 |
2016 |
1804 |
0 |
0 |