Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Unreachable
1	0	Covered	T14,T16,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151970926	149944194	0	0
AllClkBypReqTrue_A	151970926	139387	0	0
IoClkBypReqFalse_A	151970926	149861886	0	2415
IoClkBypReqTrue_A	151970926	217093	0	0
LcClkBypAckFalse_A	151970926	149954824	0	0
LcClkBypAckTrue_A	151970926	128757	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	149944194	0	0
T1	23451	23401	0	0
T2	30739	30696	0	0
T3	129517	129016	0	0
T4	91685	91515	0	0
T5	2082	1891	0	0
T6	2137	1766	0	0
T14	18008	15305	0	0
T15	1451	1383	0	0
T16	14673	6481	0	0
T17	1047	937	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	139387	0	0
T1	23451	0	0	0
T2	30739	0	0	0
T3	129517	183	0	0
T4	91685	0	0	0
T6	2137	204	0	0
T7	201140	1139	0	0
T9	0	353	0	0
T14	18008	0	0	0
T15	1451	50	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	0	29	0	0
T36	0	190	0	0
T58	0	81	0	0
T59	0	25	0	0
T94	0	58	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	149861886	0	2415
T1	23451	23399	0	3
T2	30739	30694	0	3
T3	129517	128893	0	3
T4	91685	91513	0	3
T5	2082	1889	0	3
T6	2137	1673	0	3
T14	18008	15103	0	3
T15	1451	1242	0	3
T16	14673	6379	0	3
T17	1047	935	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	217093	0	0
T1	23451	0	0	0
T2	30739	0	0	0
T3	129517	290	0	0
T4	91685	0	0	0
T6	2137	295	0	0
T7	201140	1948	0	0
T9	0	593	0	0
T14	18008	0	0	0
T15	1451	189	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T36	0	208	0	0
T58	0	268	0	0
T59	0	294	0	0
T61	0	119	0	0
T94	0	25	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	149954824	0	0
T1	23451	23401	0	0
T2	30739	30696	0	0
T3	129517	129029	0	0
T4	91685	91515	0	0
T5	2082	1891	0	0
T6	2137	1800	0	0
T14	18008	15305	0	0
T15	1451	1294	0	0
T16	14673	6481	0	0
T17	1047	937	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	128757	0	0
T1	23451	0	0	0
T2	30739	0	0	0
T3	129517	170	0	0
T4	91685	0	0	0
T6	2137	170	0	0
T7	201140	1304	0	0
T9	0	342	0	0
T14	18008	0	0	0
T15	1451	139	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T36	0	137	0	0
T58	0	187	0	0
T59	0	93	0	0
T94	0	21	0	0
T95	0	48	0	0