Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1947757840	14758	0	0
TransStop_A	1947757840	7350	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1947757840	14758	0	0
T1	375224	0	0	0
T2	491836	0	0	0
T3	2062656	64	0	0
T4	366744	0	0	0
T5	8680	4	0	0
T6	8720	0	0	0
T7	0	124	0	0
T8	0	140	0	0
T9	0	76	0	0
T14	480252	0	0	0
T15	41496	0	0	0
T16	61144	0	0	0
T17	8068	0	0	0
T24	0	40	0	0
T37	0	22	0	0
T56	0	12	0	0
T57	0	22	0	0
T60	0	65	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1947757840	7350	0	0
T1	375224	0	0	0
T2	491836	0	0	0
T3	2062656	35	0	0
T4	366744	0	0	0
T5	8680	4	0	0
T6	8720	0	0	0
T7	0	56	0	0
T8	0	71	0	0
T9	0	36	0	0
T14	480252	0	0	0
T15	41496	0	0	0
T16	61144	0	0	0
T17	8068	0	0	0
T24	0	24	0	0
T37	0	8	0	0
T56	0	2	0	0
T57	0	9	0	0
T60	0	35	0	0
T96	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486939460	3661	0	0
TransStop_A	486939460	1841	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	3661	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	30	0	0
T8	0	31	0	0
T9	0	19	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	10	0	0
T37	0	7	0	0
T56	0	5	0	0
T57	0	6	0	0
T60	0	17	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	1841	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	9	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	13	0	0
T8	0	17	0	0
T9	0	8	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	6	0	0
T37	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T60	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486939460	3668	0	0
TransStop_A	486939460	1819	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	3668	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	28	0	0
T8	0	37	0	0
T9	0	23	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	10	0	0
T37	0	4	0	0
T56	0	3	0	0
T57	0	4	0	0
T60	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	1819	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	10	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	14	0	0
T8	0	20	0	0
T9	0	10	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	7	0	0
T37	0	2	0	0
T57	0	1	0	0
T60	0	4	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486939460	3681	0	0
TransStop_A	486939460	1838	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	3681	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	33	0	0
T9	0	17	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	9	0	0
T37	0	5	0	0
T56	0	1	0	0
T57	0	6	0	0
T60	0	15	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	1838	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	9	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	17	0	0
T8	0	16	0	0
T9	0	8	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	5	0	0
T37	0	2	0	0
T57	0	3	0	0
T60	0	9	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486939460	3748	0	0
TransStop_A	486939460	1852	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	3748	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	39	0	0
T9	0	17	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	11	0	0
T37	0	6	0	0
T56	0	3	0	0
T57	0	6	0	0
T60	0	22	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939460	1852	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	7	0	0
T4	91686	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	12	0	0
T8	0	18	0	0
T9	0	10	0	0
T14	120063	0	0	0
T15	10374	0	0	0
T16	15286	0	0	0
T17	2017	0	0	0
T24	0	6	0	0
T37	0	2	0	0
T57	0	3	0	0
T60	0	12	0	0
T96	0	1	0	0