SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 303941852 | 300171764 | 0 | 0 |
gen_flops.OutputDelay_A | 303941852 | 300157644 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T14 | 2 | 2 | 0 | 0 |
T15 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303941852 | 300171764 | 0 | 0 |
T1 | 46902 | 46804 | 0 | 0 |
T2 | 61478 | 61394 | 0 | 0 |
T3 | 259034 | 258414 | 0 | 0 |
T4 | 183370 | 183032 | 0 | 0 |
T5 | 4164 | 3784 | 0 | 0 |
T6 | 4274 | 3942 | 0 | 0 |
T14 | 36016 | 30812 | 0 | 0 |
T15 | 2902 | 2868 | 0 | 0 |
T16 | 29346 | 13064 | 0 | 0 |
T17 | 2094 | 1876 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303941852 | 300157644 | 0 | 4830 |
T1 | 46902 | 46798 | 0 | 6 |
T2 | 61478 | 61388 | 0 | 6 |
T3 | 259034 | 258366 | 0 | 6 |
T4 | 183370 | 183026 | 0 | 6 |
T5 | 4164 | 3778 | 0 | 6 |
T6 | 4274 | 3936 | 0 | 6 |
T14 | 36016 | 30206 | 0 | 6 |
T15 | 2902 | 2862 | 0 | 6 |
T16 | 29346 | 12758 | 0 | 6 |
T17 | 2094 | 1870 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 151970926 | 150085882 | 0 | 0 |
gen_flops.OutputDelay_A | 151970926 | 150078822 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151970926 | 150085882 | 0 | 0 |
T1 | 23451 | 23402 | 0 | 0 |
T2 | 30739 | 30697 | 0 | 0 |
T3 | 129517 | 129207 | 0 | 0 |
T4 | 91685 | 91516 | 0 | 0 |
T5 | 2082 | 1892 | 0 | 0 |
T6 | 2137 | 1971 | 0 | 0 |
T14 | 18008 | 15406 | 0 | 0 |
T15 | 1451 | 1434 | 0 | 0 |
T16 | 14673 | 6532 | 0 | 0 |
T17 | 1047 | 938 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151970926 | 150078822 | 0 | 2415 |
T1 | 23451 | 23399 | 0 | 3 |
T2 | 30739 | 30694 | 0 | 3 |
T3 | 129517 | 129183 | 0 | 3 |
T4 | 91685 | 91513 | 0 | 3 |
T5 | 2082 | 1889 | 0 | 3 |
T6 | 2137 | 1968 | 0 | 3 |
T14 | 18008 | 15103 | 0 | 3 |
T15 | 1451 | 1431 | 0 | 3 |
T16 | 14673 | 6379 | 0 | 3 |
T17 | 1047 | 935 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 151970926 | 150085882 | 0 | 0 |
gen_flops.OutputDelay_A | 151970926 | 150078822 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151970926 | 150085882 | 0 | 0 |
T1 | 23451 | 23402 | 0 | 0 |
T2 | 30739 | 30697 | 0 | 0 |
T3 | 129517 | 129207 | 0 | 0 |
T4 | 91685 | 91516 | 0 | 0 |
T5 | 2082 | 1892 | 0 | 0 |
T6 | 2137 | 1971 | 0 | 0 |
T14 | 18008 | 15406 | 0 | 0 |
T15 | 1451 | 1434 | 0 | 0 |
T16 | 14673 | 6532 | 0 | 0 |
T17 | 1047 | 938 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151970926 | 150078822 | 0 | 2415 |
T1 | 23451 | 23399 | 0 | 3 |
T2 | 30739 | 30694 | 0 | 3 |
T3 | 129517 | 129183 | 0 | 3 |
T4 | 91685 | 91513 | 0 | 3 |
T5 | 2082 | 1889 | 0 | 3 |
T6 | 2137 | 1968 | 0 | 3 |
T14 | 18008 | 15103 | 0 | 3 |
T15 | 1451 | 1431 | 0 | 3 |
T16 | 14673 | 6379 | 0 | 3 |
T17 | 1047 | 935 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |