Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	151970926	18058503	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	18058503	0	57
T1	23451	6691	0	1
T2	30739	6984	0	1
T3	129517	6699	0	0
T4	91685	1199	0	1
T7	201140	94481	0	0
T8	0	182356	0	0
T9	0	12301	0	0
T10	0	114604	0	0
T11	0	15801	0	0
T12	0	0	0	1
T14	18008	0	0	0
T15	1451	0	0	0
T16	14673	0	0	0
T17	1047	0	0	0
T18	2146	0	0	0
T21	0	604	0	0
T22	0	0	0	1
T66	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1
T99	0	0	0	1
T100	0	0	0	1