Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fatal_err_code_reg_intg.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb 95.00 100.00 90.00
tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_jitter_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1


Line Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 + DW=1,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_jitter_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fatal_err_code_reg_intg.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
51 unreachable
52 unreachable
53 unreachable


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
95.00 100.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1


Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01Unreachable
10CoveredT1,T2,T4

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01Unreachable
10CoveredT1,T2,T4

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
95.00 90.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01Unreachable
10CoveredT5,T3,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT5,T3,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT5,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_jitter_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01CoveredT1,T2,T3
10CoveredT5,T6,T1

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT5,T6,T1

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT5,T6,T1

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01CoveredT5,T6,T1
10CoveredT6,T1,T15

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T19,T20
10CoveredT1,T19,T20
11CoveredT5,T6,T1

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT5,T6,T1

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT6,T1,T15

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT5,T6,T1
01Unreachable
10CoveredT1,T2,T4

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT5,T6,T1
1CoveredT1,T2,T4

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 34 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T1
0 Covered T5,T6,T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%