Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152919206	4657808	0	0
clk_enables_rd_A	152919206	45783	0	0
clk_hints_rd_A	152919206	41478	0	0
extclk_ctrl_rd_A	152919206	51756	0	0
extclk_ctrl_regwen_rd_A	152919206	39472	0	0
jitter_enable_rd_A	152919206	60405	0	0
jitter_regwen_rd_A	152919206	43474	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	4657808	0	0
T7	201140	95422	0	0
T8	180030	51561	0	0
T11	0	84554	0	0
T18	2146	0	0	0
T19	12405	0	0	0
T23	1610	0	0	0
T24	2504	0	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T47	0	97317	0	0
T48	0	90090	0	0
T49	0	38111	0	0
T50	0	68579	0	0
T51	0	99544	0	0
T52	0	55287	0	0
T53	0	120825	0	0
T54	1387	0	0	0
T55	1049	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	45783	0	0
T8	180030	1998	0	0
T13	0	2	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T29	0	11	0	0
T30	0	6	0	0
T32	1079	0	0	0
T37	2315	0	0	0
T47	0	1959	0	0
T49	0	695	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T56	1739	0	0	0
T94	1540	0	0	0
T120	0	9	0	0
T121	0	4	0	0
T122	0	7	0	0
T123	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	41478	0	0
T8	180030	1786	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T29	0	9	0	0
T30	0	9	0	0
T32	1079	0	0	0
T37	2315	0	0	0
T47	0	1718	0	0
T49	0	635	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T56	1739	0	0	0
T94	1540	0	0	0
T96	0	2	0	0
T120	0	6	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	51756	0	0
T8	180030	2223	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T29	0	185	0	0
T32	1079	0	0	0
T36	1998	37	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T63	0	17	0	0
T94	1540	0	0	0
T120	0	71	0	0
T124	0	28	0	0
T125	0	87	0	0
T126	0	22	0	0
T127	0	50	0	0
T128	0	32	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	39472	0	0
T8	180030	1867	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T32	1079	0	0	0
T37	2315	0	0	0
T47	0	1635	0	0
T49	0	549	0	0
T53	0	4403	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T56	1739	0	0	0
T94	1540	0	0	0
T129	0	66	0	0
T130	0	26	0	0
T131	0	2801	0	0
T132	0	3148	0	0
T133	0	2219	0	0
T134	0	1148	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	60405	0	0
T8	180030	2339	0	0
T13	0	156	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T29	0	377	0	0
T30	0	207	0	0
T32	1079	0	0	0
T37	2315	0	0	0
T47	0	2459	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T56	1739	0	0	0
T94	1540	0	0	0
T96	0	52	0	0
T120	0	238	0	0
T121	0	116	0	0
T122	0	98	0	0
T123	0	226	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152919206	43474	0	0
T8	180030	2058	0	0
T19	12405	0	0	0
T20	3080	0	0	0
T26	1356	0	0	0
T32	1079	0	0	0
T37	2315	0	0	0
T47	0	1907	0	0
T49	0	729	0	0
T53	0	5109	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T56	1739	0	0	0
T94	1540	0	0	0
T131	0	3096	0	0
T132	0	3468	0	0
T133	0	2517	0	0
T134	0	1208	0	0
T135	0	1660	0	0
T136	0	4941	0	0