Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T14
10CoveredT6,T3,T7
11CoveredT6,T15,T3

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 456926151 4666 0 0
g_div2.Div2Whole_A 456926151 5487 0 0
g_div4.Div4Stepped_A 227761071 4551 0 0
g_div4.Div4Whole_A 227761071 5179 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456926151 4666 0 0
T1 90052 0 0 0
T2 118037 0 0 0
T3 454703 8 0 0
T4 88016 0 0 0
T6 2093 7 0 0
T7 191349 47 0 0
T9 0 10 0 0
T14 115257 0 0 0
T15 9959 7 0 0
T16 14674 0 0 0
T17 1935 0 0 0
T18 0 2 0 0
T36 0 6 0 0
T58 0 7 0 0
T59 0 6 0 0
T94 0 6 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456926151 5487 0 0
T1 90052 0 0 0
T2 118037 0 0 0
T3 454703 8 0 0
T4 88016 0 0 0
T6 2093 11 0 0
T7 191349 59 0 0
T9 0 17 0 0
T14 115257 0 0 0
T15 9959 7 0 0
T16 14674 0 0 0
T17 1935 0 0 0
T18 0 5 0 0
T36 0 7 0 0
T58 0 7 0 0
T59 0 8 0 0
T94 0 9 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 227761071 4551 0 0
T1 44966 0 0 0
T2 58992 0 0 0
T3 227488 8 0 0
T4 43982 0 0 0
T6 1132 6 0 0
T7 953556 44 0 0
T9 0 10 0 0
T14 53285 0 0 0
T15 5489 7 0 0
T16 5315 0 0 0
T17 935 0 0 0
T18 0 2 0 0
T36 0 5 0 0
T58 0 7 0 0
T59 0 6 0 0
T94 0 6 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 227761071 5179 0 0
T1 44966 0 0 0
T2 58992 0 0 0
T3 227488 8 0 0
T4 43982 0 0 0
T6 1132 9 0 0
T7 953556 46 0 0
T9 0 14 0 0
T14 53285 0 0 0
T15 5489 7 0 0
T16 5315 0 0 0
T17 935 0 0 0
T18 0 4 0 0
T36 0 7 0 0
T58 0 7 0 0
T59 0 8 0 0
T94 0 9 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T14
10CoveredT6,T3,T7
11CoveredT6,T15,T3

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 456926151 4666 0 0
g_div2.Div2Whole_A 456926151 5487 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456926151 4666 0 0
T1 90052 0 0 0
T2 118037 0 0 0
T3 454703 8 0 0
T4 88016 0 0 0
T6 2093 7 0 0
T7 191349 47 0 0
T9 0 10 0 0
T14 115257 0 0 0
T15 9959 7 0 0
T16 14674 0 0 0
T17 1935 0 0 0
T18 0 2 0 0
T36 0 6 0 0
T58 0 7 0 0
T59 0 6 0 0
T94 0 6 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456926151 5487 0 0
T1 90052 0 0 0
T2 118037 0 0 0
T3 454703 8 0 0
T4 88016 0 0 0
T6 2093 11 0 0
T7 191349 59 0 0
T9 0 17 0 0
T14 115257 0 0 0
T15 9959 7 0 0
T16 14674 0 0 0
T17 1935 0 0 0
T18 0 5 0 0
T36 0 7 0 0
T58 0 7 0 0
T59 0 8 0 0
T94 0 9 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T14
10CoveredT6,T3,T7
11CoveredT6,T15,T3

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 227761071 4551 0 0
g_div4.Div4Whole_A 227761071 5179 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 227761071 4551 0 0
T1 44966 0 0 0
T2 58992 0 0 0
T3 227488 8 0 0
T4 43982 0 0 0
T6 1132 6 0 0
T7 953556 44 0 0
T9 0 10 0 0
T14 53285 0 0 0
T15 5489 7 0 0
T16 5315 0 0 0
T17 935 0 0 0
T18 0 2 0 0
T36 0 5 0 0
T58 0 7 0 0
T59 0 6 0 0
T94 0 6 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 227761071 5179 0 0
T1 44966 0 0 0
T2 58992 0 0 0
T3 227488 8 0 0
T4 43982 0 0 0
T6 1132 9 0 0
T7 953556 46 0 0
T9 0 14 0 0
T14 53285 0 0 0
T15 5489 7 0 0
T16 5315 0 0 0
T17 935 0 0 0
T18 0 4 0 0
T36 0 7 0 0
T58 0 7 0 0
T59 0 8 0 0
T94 0 9 0 0

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