Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	455912778	444	0	0
StatusRise_A	455912778	444	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455912778	444	0	0
T8	540090	0	0	0
T19	37215	0	0	0
T23	4830	13	0	0
T24	7512	0	0	0
T26	4068	0	0	0
T32	0	12	0	0
T33	0	10	0	0
T36	5994	0	0	0
T37	6945	0	0	0
T54	4161	0	0	0
T55	3147	0	0	0
T94	4620	0	0	0
T137	0	16	0	0
T138	0	3	0	0
T139	0	18	0	0
T140	0	13	0	0
T141	0	9	0	0
T142	0	18	0	0
T143	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455912778	444	0	0
T8	540090	0	0	0
T19	37215	0	0	0
T23	4830	13	0	0
T24	7512	0	0	0
T26	4068	0	0	0
T32	0	12	0	0
T33	0	10	0	0
T36	5994	0	0	0
T37	6945	0	0	0
T54	4161	0	0	0
T55	3147	0	0	0
T94	4620	0	0	0
T137	0	16	0	0
T138	0	3	0	0
T139	0	18	0	0
T140	0	13	0	0
T141	0	9	0	0
T142	0	18	0	0
T143	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151970926	149	0	0
StatusRise_A	151970926	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	149	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	4	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0
T143	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	149	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	4	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0
T143	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151970926	154	0	0
StatusRise_A	151970926	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	154	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	4	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0
T143	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	154	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	4	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0
T143	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151970926	141	0	0
StatusRise_A	151970926	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	141	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	5	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	4	0	0
T33	0	3	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	4	0	0
T141	0	5	0	0
T142	0	4	0	0
T143	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151970926	141	0	0
T8	180030	0	0	0
T19	12405	0	0	0
T23	1610	5	0	0
T24	2504	0	0	0
T26	1356	0	0	0
T32	0	4	0	0
T33	0	3	0	0
T36	1998	0	0	0
T37	2315	0	0	0
T54	1387	0	0	0
T55	1049	0	0	0
T94	1540	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	4	0	0
T141	0	5	0	0
T142	0	4	0	0
T143	0	1	0	0