Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46597	0	0
CgEnOn_A	2147483647	37397	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46597	0	0
T1	577750	3	0	0
T2	757380	3	0	0
T3	3103232	94	0	0
T4	564736	3	0	0
T5	13305	7	0	0
T6	13555	3	0	0
T7	0	30	0	0
T8	2928772	0	0	0
T14	733058	303	0	0
T15	64662	3	0	0
T16	91126	153	0	0
T17	12368	3	0	0
T19	593266	0	0	0
T23	7985	24	0	0
T24	24106	0	0	0
T26	8233	0	0	0
T32	0	20	0	0
T33	0	20	0	0
T36	9499	0	0	0
T37	31503	0	0	0
T47	0	5	0	0
T54	7231	0	0	0
T55	19416	0	0	0
T94	32991	0	0	0
T137	0	30	0	0
T138	0	5	0	0
T139	0	35	0	0
T140	0	25	0	0
T141	0	5	0	0
T142	0	40	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37397	0	0
T1	577750	0	0	0
T2	757380	0	0	0
T3	3103232	70	0	0
T4	564736	0	0	0
T5	13305	4	0	0
T6	13555	0	0	0
T7	0	202	0	0
T8	2928772	120	0	0
T9	0	12	0	0
T14	733058	0	0	0
T15	64662	0	0	0
T16	91126	0	0	0
T17	12368	0	0	0
T19	593266	0	0	0
T23	7985	36	0	0
T24	24106	10	0	0
T26	8233	0	0	0
T32	0	29	0	0
T33	0	32	0	0
T36	9499	0	0	0
T37	31503	7	0	0
T47	0	5	0	0
T54	7231	16	0	0
T55	19416	25	0	0
T56	0	5	0	0
T57	0	6	0	0
T94	32991	0	0	0
T137	0	30	0	0
T138	0	5	0	0
T139	0	35	0	0
T140	0	25	0	0
T141	0	5	0	0
T142	0	40	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227760658	165	0	0
CgEnOn_A	227760658	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227760658	165	0	0
T8	708689	0	0	0
T19	47651	0	0	0
T23	839	4	0	0
T24	2464	0	0	0
T26	838	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1025	0	0	0
T37	3229	0	0	0
T47	0	1	0	0
T54	724	0	0	0
T55	1989	0	0	0
T94	3562	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227760658	165	0	0
T8	708689	0	0	0
T19	47651	0	0	0
T23	839	4	0	0
T24	2464	0	0	0
T26	838	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1025	0	0	0
T37	3229	0	0	0
T47	0	1	0	0
T54	724	0	0	0
T55	1989	0	0	0
T94	3562	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113879664	165	0	0
CgEnOn_A	113879664	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113879664	165	0	0
CgEnOn_A	113879664	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113879664	165	0	0
CgEnOn_A	113879664	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	165	0	0
T8	354344	0	0	0
T19	23823	0	0	0
T23	419	4	0	0
T24	1232	0	0	0
T26	419	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	511	0	0	0
T37	1615	0	0	0
T47	0	1	0	0
T54	362	0	0	0
T55	995	0	0	0
T94	1780	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	456925693	165	0	0
CgEnOn_A	456925693	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456925693	165	0	0
T8	141888	0	0	0
T19	132317	0	0	0
T23	1716	4	0	0
T24	5008	0	0	0
T26	1714	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1937	0	0	0
T37	6538	0	0	0
T47	0	1	0	0
T54	1513	0	0	0
T55	4031	0	0	0
T94	6722	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456925693	157	0	0
T8	141888	0	0	0
T19	132317	0	0	0
T23	1716	4	0	0
T24	5008	0	0	0
T26	1714	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T36	1937	0	0	0
T37	6538	0	0	0
T47	0	1	0	0
T54	1513	0	0	0
T55	4031	0	0	0
T94	6722	0	0	0
T137	0	6	0	0
T138	0	1	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	1	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	152	0	0
CgEnOn_A	486939026	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	152	0	0
T8	149244	0	0	0
T11	0	1	0	0
T19	137834	0	0	0
T23	1683	4	0	0
T24	5217	0	0	0
T26	1784	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	2018	0	0	0
T37	6811	0	0	0
T54	1576	0	0	0
T55	4198	0	0	0
T94	7003	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	150	0	0
T8	149244	0	0	0
T19	137834	0	0	0
T23	1683	4	0	0
T24	5217	0	0	0
T26	1784	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	2018	0	0	0
T37	6811	0	0	0
T54	1576	0	0	0
T55	4198	0	0	0
T94	7003	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	152	0	0
CgEnOn_A	486939026	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	152	0	0
T8	149244	0	0	0
T11	0	1	0	0
T19	137834	0	0	0
T23	1683	4	0	0
T24	5217	0	0	0
T26	1784	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	2018	0	0	0
T37	6811	0	0	0
T54	1576	0	0	0
T55	4198	0	0	0
T94	7003	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	150	0	0
T8	149244	0	0	0
T19	137834	0	0	0
T23	1683	4	0	0
T24	5217	0	0	0
T26	1784	0	0	0
T32	0	5	0	0
T33	0	3	0	0
T36	2018	0	0	0
T37	6811	0	0	0
T54	1576	0	0	0
T55	4198	0	0	0
T94	7003	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	3	0	0
T142	0	6	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233762166	144	0	0
CgEnOn_A	233762166	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762166	144	0	0
T8	716675	0	0	0
T19	66161	0	0	0
T23	807	5	0	0
T24	2504	0	0	0
T26	856	0	0	0
T32	0	4	0	0
T33	0	3	0	0
T36	968	0	0	0
T37	3269	0	0	0
T54	756	0	0	0
T55	2015	0	0	0
T94	3361	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	4	0	0
T141	0	5	0	0
T142	0	4	0	0
T143	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762166	142	0	0
T8	716675	0	0	0
T19	66161	0	0	0
T23	807	5	0	0
T24	2504	0	0	0
T26	856	0	0	0
T32	0	4	0	0
T33	0	3	0	0
T36	968	0	0	0
T37	3269	0	0	0
T54	756	0	0	0
T55	2015	0	0	0
T94	3361	0	0	0
T137	0	5	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	4	0	0
T141	0	5	0	0
T142	0	4	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T32,T33
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113879664	7486	0	0
CgEnOn_A	113879664	5196	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	7486	0	0
T1	22483	1	0	0
T2	29496	1	0	0
T3	113743	26	0	0
T4	21991	1	0	0
T5	501	2	0	0
T6	565	1	0	0
T14	26640	101	0	0
T15	2744	1	0	0
T16	2658	51	0	0
T17	467	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113879664	5196	0	0
T1	22483	0	0	0
T2	29496	0	0	0
T3	113743	18	0	0
T4	21991	0	0	0
T5	501	1	0	0
T6	565	0	0	0
T7	0	59	0	0
T8	0	29	0	0
T9	0	4	0	0
T14	26640	0	0	0
T15	2744	0	0	0
T16	2658	0	0	0
T17	467	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	6	0	0
T55	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T32,T33
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227760658	7489	0	0
CgEnOn_A	227760658	5199	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227760658	7489	0	0
T1	44965	1	0	0
T2	58992	1	0	0
T3	227488	26	0	0
T4	43981	1	0	0
T5	1001	2	0	0
T6	1131	1	0	0
T14	53284	101	0	0
T15	5489	1	0	0
T16	5314	51	0	0
T17	935	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227760658	5199	0	0
T1	44965	0	0	0
T2	58992	0	0	0
T3	227488	18	0	0
T4	43981	0	0	0
T5	1001	1	0	0
T6	1131	0	0	0
T7	0	57	0	0
T8	0	30	0	0
T9	0	4	0	0
T14	53284	0	0	0
T15	5489	0	0	0
T16	5314	0	0	0
T17	935	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	5	0	0
T55	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T32,T33
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	456925693	7489	0	0
CgEnOn_A	456925693	5191	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456925693	7489	0	0
T1	90051	1	0	0
T2	118036	1	0	0
T3	454703	28	0	0
T4	88015	1	0	0
T5	2082	2	0	0
T6	2093	1	0	0
T14	115256	101	0	0
T15	9958	1	0	0
T16	14673	51	0	0
T17	1935	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456925693	5191	0	0
T1	90051	0	0	0
T2	118036	0	0	0
T3	454703	20	0	0
T4	88015	0	0	0
T5	2082	1	0	0
T6	2093	0	0	0
T7	0	56	0	0
T8	0	30	0	0
T9	0	4	0	0
T14	115256	0	0	0
T15	9958	0	0	0
T16	14673	0	0	0
T17	1935	0	0	0
T23	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T54	0	5	0	0
T55	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T32,T33
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233762166	7494	0	0
CgEnOn_A	233762166	5194	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762166	7494	0	0
T1	45027	1	0	0
T2	59020	1	0	0
T3	244642	25	0	0
T4	44009	1	0	0
T5	1041	2	0	0
T6	1046	1	0	0
T14	57630	101	0	0
T15	4979	1	0	0
T16	7337	51	0	0
T17	967	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233762166	5194	0	0
T1	45027	0	0	0
T2	59020	0	0	0
T3	244642	17	0	0
T4	44009	0	0	0
T5	1041	1	0	0
T6	1046	0	0	0
T7	0	56	0	0
T8	0	31	0	0
T9	0	4	0	0
T14	57630	0	0	0
T15	4979	0	0	0
T16	7337	0	0	0
T17	967	0	0	0
T23	0	5	0	0
T32	0	4	0	0
T33	0	3	0	0
T54	0	7	0	0
T55	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Covered	T5,T3,T7
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	3813	0	0
CgEnOn_A	486939026	3811	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3813	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	30	0	0
T8	0	31	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	10	0	0
T32	0	5	0	0
T37	0	7	0	0
T56	0	5	0	0
T57	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3811	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	30	0	0
T8	0	31	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	10	0	0
T32	0	5	0	0
T37	0	7	0	0
T56	0	5	0	0
T57	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Covered	T5,T3,T7
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	3820	0	0
CgEnOn_A	486939026	3818	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3820	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	28	0	0
T8	0	37	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	10	0	0
T32	0	5	0	0
T37	0	4	0	0
T56	0	3	0	0
T57	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3818	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	28	0	0
T8	0	37	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	10	0	0
T32	0	5	0	0
T37	0	4	0	0
T56	0	3	0	0
T57	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Covered	T5,T3,T7
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	3833	0	0
CgEnOn_A	486939026	3831	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3833	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	33	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	9	0	0
T32	0	5	0	0
T37	0	5	0	0
T56	0	1	0	0
T57	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3831	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	18	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	33	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	9	0	0
T32	0	5	0	0
T37	0	5	0	0
T56	0	1	0	0
T57	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T3
1	0	Covered	T5,T3,T7
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486939026	3900	0	0
CgEnOn_A	486939026	3898	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3900	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	39	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	11	0	0
T32	0	5	0	0
T37	0	6	0	0
T56	0	3	0	0
T57	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486939026	3898	0	0
T1	93806	0	0	0
T2	122959	0	0	0
T3	515664	14	0	0
T4	91685	0	0	0
T5	2170	1	0	0
T6	2180	0	0	0
T7	0	33	0	0
T8	0	39	0	0
T14	120062	0	0	0
T15	10373	0	0	0
T16	15286	0	0	0
T17	2016	0	0	0
T23	0	4	0	0
T24	0	11	0	0
T32	0	5	0	0
T37	0	6	0	0
T56	0	3	0	0
T57	0	6	0	0