Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331875296 1 T5 3820 T6 1974 T4 43320
auto[1] 422646 1 T5 1446 T1 3076 T15 438


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331908946 1 T5 4398 T6 1974 T4 43320
auto[1] 388996 1 T5 868 T1 1746 T15 270


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 331802760 1 T5 4274 T6 1974 T4 43320
auto[1] 495182 1 T5 992 T1 2778 T15 254


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 307321278 1 T5 4716 T6 1974 T4 43320
auto[1] 24976664 1 T5 550 T1 11118 T15 2434


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 187167088 1 T5 5064 T6 1616 T4 43304
auto[1] 145130854 1 T5 202 T6 358 T4 16


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 166004938 1 T5 3164 T6 1616 T4 43304
auto[0] auto[0] auto[0] auto[0] auto[1] 140979628 1 T5 104 T6 358 T4 16
auto[0] auto[0] auto[0] auto[1] auto[0] 31790 1 T5 372 T1 86 T15 58
auto[0] auto[0] auto[0] auto[1] auto[1] 8852 1 T5 14 T1 44 T2 24
auto[0] auto[0] auto[1] auto[0] auto[0] 20571932 1 T5 356 T1 8158 T15 1822
auto[0] auto[0] auto[1] auto[0] auto[1] 4033740 1 T1 440 T15 154 T18 204
auto[0] auto[0] auto[1] auto[1] auto[0] 51922 1 T5 106 T1 432 T15 82
auto[0] auto[0] auto[1] auto[1] auto[1] 13376 1 T1 38 T15 6 T18 12
auto[0] auto[1] auto[0] auto[0] auto[0] 49920 1 T5 54 T2 78 T26 2892
auto[0] auto[1] auto[0] auto[0] auto[1] 1644 1 T1 16 T13 64 T146 2
auto[0] auto[1] auto[0] auto[1] auto[0] 11584 1 T5 104 T2 130 T8 68
auto[0] auto[1] auto[0] auto[1] auto[1] 3304 1 T146 66 T134 40 T56 78
auto[0] auto[1] auto[1] auto[0] auto[0] 11304 1 T1 34 T15 12 T2 90
auto[0] auto[1] auto[1] auto[0] auto[1] 2794 1 T1 8 T15 10 T2 28
auto[0] auto[1] auto[1] auto[1] auto[0] 20732 1 T1 176 T15 58 T2 50
auto[0] auto[1] auto[1] auto[1] auto[1] 5300 1 T1 154 T15 52 T2 68
auto[1] auto[0] auto[0] auto[0] auto[0] 59016 1 T5 24 T1 36 T18 26
auto[1] auto[0] auto[0] auto[0] auto[1] 4592 1 T1 14 T15 8 T2 86
auto[1] auto[0] auto[0] auto[1] auto[0] 34852 1 T5 170 T1 164 T2 174
auto[1] auto[0] auto[0] auto[1] auto[1] 7500 1 T1 192 T2 76 T73 60
auto[1] auto[0] auto[1] auto[0] auto[0] 28388 1 T5 12 T1 188 T15 22
auto[1] auto[0] auto[1] auto[0] auto[1] 7718 1 T1 18 T18 2 T2 90
auto[1] auto[0] auto[1] auto[1] auto[0] 56860 1 T5 76 T1 748 T15 86
auto[1] auto[0] auto[1] auto[1] auto[1] 13842 1 T1 60 T18 66 T2 118
auto[1] auto[1] auto[0] auto[0] auto[0] 56548 1 T5 90 T1 176 T15 8
auto[1] auto[1] auto[0] auto[0] auto[1] 6022 1 T5 16 T1 52 T2 98
auto[1] auto[1] auto[0] auto[1] auto[0] 49084 1 T5 536 T1 362 T18 188
auto[1] auto[1] auto[0] auto[1] auto[1] 12004 1 T5 68 T1 104 T11 254
auto[1] auto[1] auto[1] auto[0] auto[0] 45554 1 T1 140 T15 32 T18 30
auto[1] auto[1] auto[1] auto[0] auto[1] 11558 1 T1 8 T15 2 T18 24
auto[1] auto[1] auto[1] auto[1] auto[0] 82664 1 T1 516 T15 58 T18 74
auto[1] auto[1] auto[1] auto[1] auto[1] 18980 1 T15 38 T2 388 T73 42

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%