Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 93.75 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

16 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack 0.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 6 0 0.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
false 0 1 1
true 0 1 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 177 1 T7 1 T118 1 T76 1
others[1] 178 1 T30 1 T80 2 T172 1
others[2] 3595 1 T7 6 T30 16 T17 1
others[3] 254 1 T38 4 T118 1 T120 1
false 798 1 T7 2 T30 4 T38 4
true 2475 1 T7 1 T30 9 T17 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T119 1 T94 1 T173 1
others[1] 73 1 T30 1 T38 1 T174 1
others[2] 3538 1 T7 5 T30 16 T17 1
others[3] 179 1 T30 3 T38 1 T175 1
false 553 1 T118 2 T4 18 T80 7
true 3040 1 T7 5 T30 10 T17 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 633 1 T6 1 T1 3 T23 2
others[1] 629 1 T6 1 T1 1 T20 3
others[2] 556 1 T6 2 T1 2 T20 1
others[3] 1024 1 T5 3 T6 5 T1 4
false 4111 1 T5 5 T6 10 T1 12
true 997 1 T5 2 T6 1 T1 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 558 1 T1 1 T20 1 T23 1
others[1] 601 1 T5 1 T6 1 T1 1
others[2] 608 1 T5 1 T6 4 T1 4
others[3] 1005 1 T5 2 T6 2 T1 4
false 4126 1 T5 5 T6 10 T1 12
true 1052 1 T5 1 T6 3 T1 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 603 1 T6 2 T1 6 T23 2
others[1] 616 1 T5 1 T6 2 T20 1
others[2] 586 1 T5 2 T6 1 T20 2
others[3] 1021 1 T6 3 T1 3 T20 2
false 4114 1 T5 5 T6 10 T1 12
true 1010 1 T5 2 T6 2 T1 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2470 1 T39 19 T40 19 T80 19
others[1] 390 1 T39 3 T40 3 T80 3
others[2] 390 1 T39 3 T40 3 T80 3
others[3] 650 1 T39 5 T40 5 T80 5
false 130 1 T39 1 T40 1 T80 1
true 130 1 T39 1 T40 1 T80 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 588 1 T6 1 T1 1 T20 2
others[1] 608 1 T5 2 T1 1 T20 3
others[2] 608 1 T6 3 T1 2 T23 1
others[3] 1083 1 T5 1 T6 3 T1 6
false 4119 1 T5 5 T6 10 T1 12
true 944 1 T5 2 T6 3 T1 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 644 1 T6 1 T1 1 T23 2
others[1] 624 1 T5 2 T6 2 T1 4
others[2] 621 1 T5 1 T6 5 T1 3
others[3] 976 1 T1 2 T20 1 T31 2
false 4125 1 T5 5 T6 10 T1 12
true 960 1 T5 2 T6 2 T1 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1439 1 T7 3 T30 5 T24 1
others[1] 1464 1 T7 1 T38 3 T118 1
others[2] 1485 1 T7 1 T30 4 T38 2
others[3] 2552 1 T7 1 T30 4 T17 1
false 5434 1 T7 1 T8 1 T5 1
true 3985 1 T7 4 T30 7 T38 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1886 1 T24 1 T38 4 T118 5
others[1] 2026 1 T7 1 T30 7 T38 4
others[2] 1850 1 T7 1 T30 8 T38 1
others[3] 3264 1 T7 1 T30 7 T38 4
false 6119 1 T7 3 T8 1 T5 1
true 6633 1 T7 4 T30 13 T17 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 698 1 T26 6 T21 3 T39 1
others[1] 95 1 T26 1 T150 4 T176 2
others[2] 98 1 T26 5 T21 1 T150 3
others[3] 188 1 T26 7 T21 1 T150 7
false 10657 1 T7 1 T8 1 T26 8
true 11939 1 T7 2 T8 1 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 699 1 T26 4 T39 1 T2 7
others[1] 104 1 T26 4 T21 3 T150 7
others[2] 99 1 T26 2 T21 1 T150 4
others[3] 177 1 T26 9 T21 1 T150 1
false 10616 1 T7 1 T8 1 T26 12
true 11875 1 T7 2 T8 1 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 700 1 T26 4 T21 1 T39 1
others[1] 127 1 T26 5 T150 3 T176 4
others[2] 94 1 T26 4 T21 2 T150 5
others[3] 158 1 T26 6 T21 2 T150 9
false 10732 1 T7 1 T8 1 T26 11
true 11995 1 T7 2 T8 1 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 700 1 T26 3 T21 1 T39 1
others[1] 107 1 T26 5 T21 2 T150 3
others[2] 95 1 T26 3 T21 1 T150 3
others[3] 177 1 T26 8 T21 1 T150 6
false 10625 1 T7 1 T26 9 T27 1
true 11918 1 T7 2 T8 1 T5 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 940 1 T30 1 T38 3 T2 9
others[1] 989 1 T30 2 T38 3 T2 11
others[2] 910 1 T30 1 T38 1 T2 10
others[3] 1533 1 T7 1 T30 3 T38 3
false 5082 1 T7 1 T8 1 T5 1
true 5193 1 T7 1 T30 9 T17 1

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