Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	644157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3827398

1

T7

7

T8

1

T5

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1097099	1			T7	5		T5	11		T26	76
values[0x0]	1548811	1			T7	6		T5	54		T26	32
values[0x1]	1825645	1			T7	5		T8	3		T5	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4121287

1

T7

9

T8

3

T5

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18070	1			T1	2		T2	614		T40	1
valid_sources[0x01]	17195	1			T6	2		T1	3		T23	1
valid_sources[0x02]	16664	1			T5	2		T2	549		T4	4
valid_sources[0x03]	16729	1			T6	2		T2	561		T40	1
valid_sources[0x04]	18714	1			T6	1		T31	1		T118	8
valid_sources[0x05]	15934	1			T6	2		T2	580		T4	3
valid_sources[0x06]	16688	1			T6	1		T2	568		T40	1
valid_sources[0x07]	17774	1			T26	1		T39	1		T2	580
valid_sources[0x08]	17547	1			T7	1		T6	7		T31	1
valid_sources[0x09]	15503	1			T6	1		T2	551		T4	3
valid_sources[0x0a]	17332	1			T5	2		T26	3		T1	1
valid_sources[0x0b]	18033	1			T7	1		T26	5		T20	1
valid_sources[0x0c]	17190	1			T1	1		T23	1		T39	7
valid_sources[0x0d]	16072	1			T6	1		T1	3		T18	1
valid_sources[0x0e]	17535	1			T5	2		T6	1		T2	623
valid_sources[0x0f]	17570	1			T30	1		T2	550		T4	1
valid_sources[0x10]	18278	1			T6	1		T1	9		T2	610
valid_sources[0x11]	17468	1			T5	2		T1	1		T31	1
valid_sources[0x12]	16902	1			T6	2		T23	2		T2	602
valid_sources[0x13]	17316	1			T30	2		T18	1		T38	1
valid_sources[0x14]	15614	1			T30	1		T1	1		T31	1
valid_sources[0x15]	18357	1			T1	7		T23	1		T2	626
valid_sources[0x16]	17526	1			T30	2		T1	1		T20	1
valid_sources[0x17]	17786	1			T6	2		T1	2		T2	581
valid_sources[0x18]	16594	1			T7	1		T26	3		T23	1
valid_sources[0x19]	16815	1			T1	3		T20	9		T31	2
valid_sources[0x1a]	18390	1			T5	2		T30	1		T6	3
valid_sources[0x1b]	15806	1			T5	1		T26	3		T6	4
valid_sources[0x1c]	15741	1			T6	2		T1	4		T38	1
valid_sources[0x1d]	16926	1			T39	8		T2	576		T4	2
valid_sources[0x1e]	17757	1			T6	1		T23	1		T2	583
valid_sources[0x1f]	16069	1			T1	1		T2	573		T4	7
valid_sources[0x20]	15934	1			T5	1		T26	6		T6	3
valid_sources[0x21]	19847	1			T30	1		T1	2		T2	624
valid_sources[0x22]	17536	1			T5	1		T31	4		T2	555
valid_sources[0x23]	17779	1			T6	3		T23	2		T2	587
valid_sources[0x24]	16787	1			T5	1		T2	580		T4	2
valid_sources[0x25]	18009	1			T1	7		T20	3		T2	589
valid_sources[0x26]	17489	1			T30	1		T6	1		T23	1
valid_sources[0x27]	15704	1			T26	1		T6	2		T23	1
valid_sources[0x28]	16853	1			T23	2		T2	588		T40	1
valid_sources[0x29]	17628	1			T6	1		T2	565		T40	4
valid_sources[0x2a]	15216	1			T2	620		T4	4		T77	2
valid_sources[0x2b]	16164	1			T1	4		T23	1		T38	1
valid_sources[0x2c]	15806	1			T26	2		T2	576		T4	5
valid_sources[0x2d]	15380	1			T6	2		T31	2		T2	629
valid_sources[0x2e]	17637	1			T6	3		T38	1		T2	574
valid_sources[0x2f]	17939	1			T6	2		T2	620		T4	2
valid_sources[0x30]	20659	1			T6	3		T21	1		T23	2
valid_sources[0x31]	16116	1			T23	1		T2	566		T40	1
valid_sources[0x32]	21010	1			T5	1		T2	582		T32	1
valid_sources[0x33]	18187	1			T1	2		T19	1		T20	1
valid_sources[0x34]	16945	1			T5	1		T2	601		T4	7
valid_sources[0x35]	16279	1			T5	3		T23	3		T2	565
valid_sources[0x36]	18406	1			T5	1		T20	2		T38	1
valid_sources[0x37]	16481	1			T5	1		T23	3		T38	1
valid_sources[0x38]	17182	1			T1	1		T20	2		T2	605
valid_sources[0x39]	17210	1			T6	1		T2	608		T40	2
valid_sources[0x3a]	18412	1			T1	1		T20	3		T38	1
valid_sources[0x3b]	17857	1			T26	2		T2	580		T32	1
valid_sources[0x3c]	17573	1			T5	1		T6	2		T20	3
valid_sources[0x3d]	18048	1			T7	1		T1	1		T18	3
valid_sources[0x3e]	16882	1			T7	1		T5	1		T26	8
valid_sources[0x3f]	17934	1			T5	2		T30	1		T23	4
valid_sources[0x40]	17357	1			T38	1		T31	3		T2	556
valid_sources[0x41]	18064	1			T23	1		T2	554		T4	6
valid_sources[0x42]	16664	1			T5	1		T30	1		T38	1
valid_sources[0x43]	17024	1			T26	1		T30	2		T1	6
valid_sources[0x44]	19112	1			T5	1		T1	1		T2	559
valid_sources[0x45]	16461	1			T6	2		T1	1		T38	2
valid_sources[0x46]	17334	1			T5	1		T2	565		T40	1
valid_sources[0x47]	18393	1			T5	1		T27	3		T1	9
valid_sources[0x48]	17491	1			T5	2		T26	3		T6	5
valid_sources[0x49]	15754	1			T1	7		T23	1		T2	590
valid_sources[0x4a]	17856	1			T5	1		T20	3		T21	4
valid_sources[0x4b]	18798	1			T18	1		T23	2		T2	558
valid_sources[0x4c]	18015	1			T18	1		T20	1		T23	1
valid_sources[0x4d]	17019	1			T5	1		T2	603		T4	6
valid_sources[0x4e]	18017	1			T20	1		T23	1		T31	1
valid_sources[0x4f]	17671	1			T20	10		T23	1		T2	583
valid_sources[0x50]	17977	1			T1	2		T19	9		T31	2
valid_sources[0x51]	16896	1			T5	1		T22	98		T23	3
valid_sources[0x52]	17708	1			T1	2		T23	1		T31	1
valid_sources[0x53]	18090	1			T5	1		T26	2		T6	2
valid_sources[0x54]	17088	1			T6	1		T20	1		T31	1
valid_sources[0x55]	17615	1			T7	1		T2	578		T4	4
valid_sources[0x56]	16653	1			T6	1		T2	595		T4	2
valid_sources[0x57]	18875	1			T26	3		T30	1		T6	1
valid_sources[0x58]	16451	1			T5	1		T6	1		T23	3
valid_sources[0x59]	19044	1			T26	3		T2	576		T40	2
valid_sources[0x5a]	16607	1			T5	2		T26	2		T6	1
valid_sources[0x5b]	18358	1			T23	1		T2	572		T4	4
valid_sources[0x5c]	18149	1			T5	1		T20	6		T23	2
valid_sources[0x5d]	16947	1			T1	2		T2	557		T4	2
valid_sources[0x5e]	17538	1			T19	1		T39	4		T2	563
valid_sources[0x5f]	18955	1			T26	3		T23	1		T2	603
valid_sources[0x60]	16588	1			T5	1		T1	1		T19	2
valid_sources[0x61]	16662	1			T5	1		T6	2		T18	5
valid_sources[0x62]	17602	1			T5	1		T23	1		T2	593
valid_sources[0x63]	17635	1			T7	1		T5	3		T6	2
valid_sources[0x64]	16112	1			T26	12		T23	1		T2	586
valid_sources[0x65]	18087	1			T23	1		T2	588		T4	3
valid_sources[0x66]	18507	1			T23	4		T2	574		T4	4
valid_sources[0x67]	17025	1			T5	4		T1	2		T2	579
valid_sources[0x68]	17791	1			T2	557		T32	2		T4	5
valid_sources[0x69]	16944	1			T7	1		T6	1		T1	1
valid_sources[0x6a]	17528	1			T6	2		T2	578		T4	1
valid_sources[0x6b]	17744	1			T2	578		T32	3		T10	186
valid_sources[0x6c]	14725	1			T39	20		T2	559		T40	1
valid_sources[0x6d]	16924	1			T5	1		T6	2		T1	4
valid_sources[0x6e]	18178	1			T6	4		T38	1		T2	533
valid_sources[0x6f]	16728	1			T5	2		T6	5		T1	8
valid_sources[0x70]	16268	1			T23	2		T2	566		T4	2
valid_sources[0x71]	15496	1			T5	2		T1	3		T23	1
valid_sources[0x72]	17846	1			T6	1		T1	1		T23	3
valid_sources[0x73]	17127	1			T7	1		T27	1		T23	1
valid_sources[0x74]	16067	1			T21	2		T2	567		T32	1
valid_sources[0x75]	18585	1			T1	3		T17	1		T20	1
valid_sources[0x76]	17845	1			T18	1		T23	1		T2	606
valid_sources[0x77]	16354	1			T6	3		T1	4		T23	2
valid_sources[0x78]	18525	1			T26	3		T23	3		T31	1
valid_sources[0x79]	18117	1			T6	1		T1	4		T23	3
valid_sources[0x7a]	18659	1			T5	1		T6	1		T23	2
valid_sources[0x7b]	19452	1			T1	2		T20	5		T23	1
valid_sources[0x7c]	18180	1			T26	2		T6	6		T21	1
valid_sources[0x7d]	16241	1			T5	1		T6	1		T20	2
valid_sources[0x7e]	16407	1			T5	2		T23	1		T2	587
valid_sources[0x7f]	18949	1			T5	1		T20	2		T38	1
valid_sources[0x80]	17974	1			T5	1		T20	2		T23	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

965179

1

T7

3

T5

5

T26

37

values[0x0]

all_enables

biggest_size

1453598

1

T7

3

T5

33

T26

9

values[0x1]

all_enables

biggest_size

1408621

1

T7

1

T8

1

T5

15