Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T28,T25,T37
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	958068912	13472	0	0
GateOpen_A	958068912	20293	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958068912	13472	0	0
T1	314263	0	0	0
T2	0	145	0	0
T6	195521	0	0	0
T17	2756	0	0	0
T18	3077	0	0	0
T19	3295	0	0	0
T20	135588	0	0	0
T25	0	18	0	0
T27	3365	8	0	0
T28	2808	4	0	0
T29	3049	18	0	0
T30	14280	0	0	0
T37	0	12	0	0
T39	0	4	0	0
T40	0	4	0	0
T78	0	5	0	0
T79	0	43	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958068912	20293	0	0
T1	314263	4	0	0
T5	124687	4	0	0
T6	195521	4	0	0
T17	2756	4	0	0
T18	3077	0	0	0
T21	0	4	0	0
T25	0	22	0	0
T26	56913	0	0	0
T27	3365	12	0	0
T28	2808	8	0	0
T29	3049	18	0	0
T30	14280	0	0	0
T31	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T28,T25,T37
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	105534760	3203	0	0
GateOpen_A	105534760	4908	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534760	3203	0	0
T1	34898	0	0	0
T2	0	35	0	0
T6	19787	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T25	0	5	0	0
T27	352	2	0	0
T28	290	1	0	0
T29	321	4	0	0
T30	1704	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	1	0	0
T79	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534760	4908	0	0
T1	34898	1	0	0
T5	13841	1	0	0
T6	19787	1	0	0
T17	291	1	0	0
T18	338	0	0	0
T21	0	1	0	0
T25	0	6	0	0
T26	6320	0	0	0
T27	352	3	0	0
T28	290	2	0	0
T29	321	4	0	0
T30	1704	0	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T28,T25,T37
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	211070431	3439	0	0
GateOpen_A	211070431	5144	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	3439	0	0
T1	69795	0	0	0
T2	0	34	0	0
T6	39573	0	0	0
T17	582	0	0	0
T18	676	0	0	0
T19	706	0	0	0
T20	26922	0	0	0
T25	0	5	0	0
T27	703	2	0	0
T28	580	1	0	0
T29	642	4	0	0
T30	3408	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	2	0	0
T79	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	5144	0	0
T1	69795	1	0	0
T5	27682	1	0	0
T6	39573	1	0	0
T17	582	1	0	0
T18	676	0	0	0
T21	0	1	0	0
T25	0	6	0	0
T26	12639	0	0	0
T27	703	3	0	0
T28	580	2	0	0
T29	642	4	0	0
T30	3408	0	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T28,T25,T37
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	423910728	3426	0	0
GateOpen_A	423910728	5132	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	3426	0	0
T1	139711	0	0	0
T2	0	37	0	0
T6	79252	0	0	0
T17	1255	0	0	0
T18	1376	0	0	0
T19	1490	0	0	0
T20	53869	0	0	0
T25	0	5	0	0
T27	1540	2	0	0
T28	1294	1	0	0
T29	1391	5	0	0
T30	6112	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	1	0	0
T79	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	5132	0	0
T1	139711	1	0	0
T5	55442	1	0	0
T6	79252	1	0	0
T17	1255	1	0	0
T18	1376	0	0	0
T21	0	1	0	0
T25	0	6	0	0
T26	25302	0	0	0
T27	1540	3	0	0
T28	1294	2	0	0
T29	1391	5	0	0
T30	6112	0	0	0
T31	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T28,T25,T37
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	217552993	3404	0	0
GateOpen_A	217552993	5109	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552993	3404	0	0
T1	69859	0	0	0
T2	0	39	0	0
T6	56909	0	0	0
T17	628	0	0	0
T18	687	0	0	0
T19	746	0	0	0
T20	41336	0	0	0
T25	0	3	0	0
T27	770	2	0	0
T28	644	1	0	0
T29	695	5	0	0
T30	3056	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	1	0	0
T79	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552993	5109	0	0
T1	69859	1	0	0
T5	27722	1	0	0
T6	56909	1	0	0
T17	628	1	0	0
T18	687	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T26	12652	0	0	0
T27	770	3	0	0
T28	644	2	0	0
T29	695	5	0	0
T30	3056	0	0	0
T31	0	1	0	0