Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	861631900	73294	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	861631900	73294	0	0
T1	87320	32	0	0
T2	0	1377	0	0
T3	0	682	0	0
T10	0	406	0	0
T11	0	552	0	0
T12	0	125	0	0
T13	0	1050	0	0
T14	0	193	0	0
T15	0	2171	0	0
T16	0	651	0	0
T17	6270	0	0	0
T18	7160	0	0	0
T19	6365	0	0	0
T20	430570	0	0	0
T21	5545	0	0	0
T22	9130	0	0	0
T23	114505	0	0	0
T24	5825	0	0	0
T25	5895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172326380	10711	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	10711	0	0
T1	17464	6	0	0
T2	0	178	0	0
T3	0	90	0	0
T10	0	64	0	0
T11	0	88	0	0
T12	0	17	0	0
T13	0	137	0	0
T14	0	31	0	0
T15	0	321	0	0
T16	0	107	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	1165	0	0	0
T25	1179	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172326380	10539	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	10539	0	0
T1	17464	6	0	0
T2	0	197	0	0
T3	0	87	0	0
T10	0	64	0	0
T11	0	85	0	0
T12	0	17	0	0
T13	0	134	0	0
T14	0	31	0	0
T15	0	274	0	0
T16	0	107	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	1165	0	0	0
T25	1179	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172326380	14773	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	14773	0	0
T1	17464	6	0	0
T2	0	272	0	0
T3	0	138	0	0
T10	0	82	0	0
T11	0	112	0	0
T12	0	28	0	0
T13	0	209	0	0
T14	0	39	0	0
T15	0	427	0	0
T16	0	133	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	1165	0	0	0
T25	1179	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172326380	14708	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	14708	0	0
T1	17464	6	0	0
T2	0	274	0	0
T3	0	137	0	0
T10	0	82	0	0
T11	0	112	0	0
T12	0	24	0	0
T13	0	215	0	0
T14	0	39	0	0
T15	0	443	0	0
T16	0	132	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	1165	0	0	0
T25	1179	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172326380	22563	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	22563	0	0
T1	17464	8	0	0
T2	0	456	0	0
T3	0	230	0	0
T10	0	114	0	0
T11	0	155	0	0
T12	0	39	0	0
T13	0	355	0	0
T14	0	53	0	0
T15	0	706	0	0
T16	0	172	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	1165	0	0	0
T25	1179	0	0	0