Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T2,T4,T10

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	172326380	168968543	0	0
AllClkBypReqTrue_A	172326380	135046	0	0
IoClkBypReqFalse_A	172326380	168884946	0	2415
IoClkBypReqTrue_A	172326380	213923	0	0
LcClkBypAckFalse_A	172326380	168976632	0	0
LcClkBypAckTrue_A	172326380	126957	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	168968543	0	0
T1	17464	17440	0	0
T5	16748	16686	0	0
T6	29893	29841	0	0
T7	1256	1140	0	0
T8	798	793	0	0
T26	3689	3677	0	0
T27	1588	1377	0	0
T28	1364	1110	0	0
T29	1332	1162	0	0
T30	1845	1563	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	135046	0	0
T1	17464	0	0	0
T2	0	1170	0	0
T5	16748	0	0	0
T6	29893	0	0	0
T7	1256	87	0	0
T8	798	0	0	0
T10	0	1573	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	212	0	0
T38	0	68	0	0
T76	0	78	0	0
T80	0	575	0	0
T117	0	43	0	0
T118	0	139	0	0
T119	0	172	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	168884946	0	2415
T1	17464	17438	0	3
T5	16748	16684	0	3
T6	29893	29839	0	3
T7	1256	1189	0	3
T8	798	791	0	3
T26	3689	3675	0	3
T27	1588	1375	0	3
T28	1364	1108	0	3
T29	1332	1160	0	3
T30	1845	1380	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	213923	0	0
T1	17464	0	0	0
T2	0	1936	0	0
T5	16748	0	0	0
T6	29893	0	0	0
T7	1256	36	0	0
T8	798	0	0	0
T10	0	2160	0	0
T17	0	29	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	393	0	0
T38	0	312	0	0
T76	0	57	0	0
T80	0	779	0	0
T117	0	47	0	0
T120	0	185	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	168976632	0	0
T1	17464	17440	0	0
T5	16748	16686	0	0
T6	29893	29841	0	0
T7	1256	1195	0	0
T8	798	793	0	0
T26	3689	3677	0	0
T27	1588	1377	0	0
T28	1364	1110	0	0
T29	1332	1162	0	0
T30	1845	1554	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	126957	0	0
T1	17464	0	0	0
T2	0	1280	0	0
T5	16748	0	0	0
T6	29893	0	0	0
T7	1256	32	0	0
T8	798	0	0	0
T10	0	1264	0	0
T17	0	1	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	221	0	0
T38	0	185	0	0
T76	0	23	0	0
T80	0	392	0	0
T117	0	39	0	0
T120	0	103	0	0