Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1814379456	15905	0	0
TransStop_A	1814379456	8178	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1814379456	15905	0	0
T1	582144	0	0	0
T2	0	247	0	0
T6	450232	0	0	0
T10	0	157	0	0
T17	5232	0	0	0
T18	5732	0	0	0
T19	6212	5	0	0
T21	0	12	0	0
T22	0	23	0	0
T26	105428	32	0	0
T27	6412	0	0	0
T28	5476	0	0	0
T29	5796	0	0	0
T30	25468	0	0	0
T39	0	4	0	0
T40	0	4	0	0
T77	0	29	0	0
T80	0	88	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1814379456	8178	0	0
T1	582144	0	0	0
T2	0	125	0	0
T6	450232	0	0	0
T10	0	89	0	0
T17	5232	0	0	0
T18	5732	0	0	0
T19	6212	3	0	0
T21	0	5	0	0
T22	0	14	0	0
T26	105428	17	0	0
T27	6412	0	0	0
T28	5476	0	0	0
T29	5796	0	0	0
T30	25468	0	0	0
T39	0	4	0	0
T40	0	4	0	0
T77	0	14	0	0
T80	0	53	0	0
T121	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	453594864	3996	0	0
TransStop_A	453594864	2029	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	3996	0	0
T1	145536	0	0	0
T2	0	61	0	0
T6	112558	0	0	0
T10	0	42	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	3	0	0
T22	0	6	0	0
T26	26357	6	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	4	0	0
T80	0	25	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	2029	0	0
T1	145536	0	0	0
T2	0	31	0	0
T6	112558	0	0	0
T10	0	22	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	1	0	0
T22	0	5	0	0
T26	26357	3	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	1	0	0
T80	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	453594864	3970	0	0
TransStop_A	453594864	2033	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	3970	0	0
T1	145536	0	0	0
T2	0	65	0	0
T6	112558	0	0	0
T10	0	33	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	2	0	0
T21	0	4	0	0
T22	0	4	0	0
T26	26357	5	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	10	0	0
T80	0	19	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	2033	0	0
T1	145536	0	0	0
T2	0	34	0	0
T6	112558	0	0	0
T10	0	18	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T26	26357	3	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	5	0	0
T80	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	453594864	3952	0	0
TransStop_A	453594864	2055	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	3952	0	0
T1	145536	0	0	0
T2	0	52	0	0
T6	112558	0	0	0
T10	0	41	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	2	0	0
T22	0	6	0	0
T26	26357	7	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	6	0	0
T80	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	2055	0	0
T1	145536	0	0	0
T2	0	27	0	0
T6	112558	0	0	0
T10	0	25	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T26	26357	3	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	3	0	0
T80	0	14	0	0
T121	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	453594864	3987	0	0
TransStop_A	453594864	2061	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	3987	0	0
T1	145536	0	0	0
T2	0	69	0	0
T6	112558	0	0	0
T10	0	41	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	3	0	0
T22	0	7	0	0
T26	26357	14	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	9	0	0
T80	0	21	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594864	2061	0	0
T1	145536	0	0	0
T2	0	33	0	0
T6	112558	0	0	0
T10	0	24	0	0
T17	1308	0	0	0
T18	1433	0	0	0
T19	1553	1	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	26357	8	0	0
T27	1603	0	0	0
T28	1369	0	0	0
T29	1449	0	0	0
T30	6367	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T77	0	5	0	0
T80	0	11	0	0