Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	172326380	17346386	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	17346386	0	60
T1	17464	2271	0	1
T2	0	159159	0	0
T3	0	81091	0	1
T5	16748	777	0	1
T6	29893	0	0	0
T10	0	30895	0	0
T11	0	38033	0	0
T12	0	12278	0	1
T13	0	718446	0	0
T14	0	12143	0	1
T15	0	258425	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T122	0	0	0	1
T123	0	0	0	1
T124	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1