Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173262092	5632602	0	0
clk_enables_rd_A	173262092	51044	0	0
clk_hints_rd_A	173262092	44876	0	0
extclk_ctrl_rd_A	173262092	56751	0	0
extclk_ctrl_regwen_rd_A	173262092	42851	0	0
jitter_enable_rd_A	173262092	62486	0	0
jitter_regwen_rd_A	173262092	48101	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	5632602	0	0
T2	434148	208358	0	0
T3	190301	0	0	0
T4	118713	0	0	0
T10	0	58456	0	0
T11	0	159555	0	0
T13	0	120646	0	0
T15	0	229773	0	0
T16	0	52460	0	0
T32	13422	0	0	0
T37	1355	0	0	0
T40	1694	0	0	0
T72	0	49730	0	0
T73	0	137701	0	0
T74	0	112201	0	0
T75	0	191366	0	0
T76	1365	0	0	0
T77	2594	0	0	0
T78	1383	0	0	0
T79	1239	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	51044	0	0
T3	190301	0	0	0
T4	118713	0	0	0
T10	196757	2558	0	0
T13	0	4983	0	0
T16	0	2167	0	0
T37	1355	0	0	0
T40	1694	5	0	0
T55	0	1	0	0
T72	0	1826	0	0
T74	0	2197	0	0
T76	1365	0	0	0
T77	2594	0	0	0
T78	1383	0	0	0
T79	1239	0	0	0
T80	0	5	0	0
T116	0	2	0	0
T121	0	2	0	0
T145	1073	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	44876	0	0
T10	196757	1836	0	0
T11	313418	0	0	0
T13	0	3951	0	0
T16	0	1963	0	0
T55	0	1	0	0
T72	0	1715	0	0
T74	0	1930	0	0
T80	185078	2	0	0
T119	1620	0	0	0
T120	1825	0	0	0
T121	2074	6	0	0
T145	1073	0	0	0
T146	0	4	0	0
T147	0	5	0	0
T148	1208	0	0	0
T149	2707	0	0	0
T150	2915	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	56751	0	0
T1	17464	0	0	0
T4	0	146	0	0
T6	29893	0	0	0
T10	0	2796	0	0
T13	0	4814	0	0
T16	0	2341	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T22	1826	0	0	0
T23	22901	0	0	0
T24	0	9	0	0
T30	1845	29	0	0
T72	0	2160	0	0
T80	0	108	0	0
T117	0	4	0	0
T151	0	37	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	42851	0	0
T3	190301	0	0	0
T4	118713	68	0	0
T10	196757	2019	0	0
T13	0	4074	0	0
T16	0	1702	0	0
T37	1355	0	0	0
T72	0	1879	0	0
T74	0	2006	0	0
T76	1365	0	0	0
T77	2594	0	0	0
T78	1383	0	0	0
T79	1239	0	0	0
T81	0	35	0	0
T115	0	25	0	0
T120	1825	0	0	0
T145	1073	0	0	0
T152	0	9	0	0
T153	0	20	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	62486	0	0
T3	190301	0	0	0
T4	118713	0	0	0
T10	196757	3120	0	0
T13	0	5436	0	0
T16	0	2434	0	0
T37	1355	0	0	0
T40	1694	114	0	0
T72	0	1615	0	0
T74	0	2573	0	0
T76	1365	0	0	0
T77	2594	0	0	0
T78	1383	0	0	0
T79	1239	0	0	0
T80	0	132	0	0
T121	0	88	0	0
T145	1073	0	0	0
T146	0	105	0	0
T154	0	139	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	48101	0	0
T10	196757	2148	0	0
T11	313418	0	0	0
T13	0	4479	0	0
T16	0	2065	0	0
T72	0	2013	0	0
T74	0	2331	0	0
T80	185078	0	0	0
T119	1620	0	0	0
T120	1825	0	0	0
T121	2074	0	0	0
T145	1073	0	0	0
T148	1208	0	0	0
T149	2707	0	0	0
T150	2915	0	0	0
T155	0	2474	0	0
T156	0	2550	0	0
T157	0	4772	0	0
T158	0	5309	0	0
T159	0	1421	0	0