Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1732620920	1537799	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1732620920	278325	0	0
SrcBusyKnown_A	1732620920	1699360410	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732620920	1537799	0	0
T1	174640	603	0	0
T2	0	38337	0	0
T3	0	2611	0	0
T4	0	4446	0	0
T5	167480	376	0	0
T6	298930	680	0	0
T17	12540	0	0	0
T18	14320	0	0	0
T20	0	1185	0	0
T23	0	460	0	0
T26	36890	0	0	0
T27	15880	0	0	0
T28	13640	0	0	0
T29	13320	0	0	0
T30	18450	0	0	0
T31	0	582	0	0
T32	0	160	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	919592	918522	0	0
T5	364882	363664	0	0
T6	616154	614976	0	0
T7	31990	31400	0	0
T8	100968	100478	0	0
T26	166538	166048	0	0
T27	9928	8794	0	0
T28	8348	6938	0	0
T29	8992	7998	0	0
T30	41292	39932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732620920	278325	0	0
T1	174640	240	0	0
T2	0	4505	0	0
T3	0	340	0	0
T4	0	523	0	0
T5	167480	100	0	0
T6	298930	200	0	0
T17	12540	0	0	0
T18	14320	0	0	0
T20	0	140	0	0
T23	0	140	0	0
T26	36890	0	0	0
T27	15880	0	0	0
T28	13640	0	0	0
T29	13320	0	0	0
T30	18450	0	0	0
T31	0	100	0	0
T32	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1732620920	1699360410	0	0
T1	174640	174410	0	0
T5	167480	166870	0	0
T6	298930	298420	0	0
T7	12560	12280	0	0
T8	7980	7940	0	0
T26	36890	36780	0	0
T27	15880	13780	0	0
T28	13640	11110	0	0
T29	13320	11630	0	0
T30	18450	17760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	94888	0	0
DstReqKnown_A	426191130	421361137	0	0
SrcAckBusyChk_A	173262092	24893	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	94888	0	0
T1	17464	56	0	0
T2	0	2307	0	0
T3	0	163	0	0
T4	0	214	0	0
T5	16748	29	0	0
T6	29893	50	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	70	0	0
T23	0	35	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	39	0	0
T32	0	10	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426191130	421361137	0	0
T1	139710	139520	0	0
T5	55442	55239	0	0
T6	79252	79049	0	0
T7	4825	4717	0	0
T8	15342	15262	0	0
T26	25302	25222	0	0
T27	1539	1336	0	0
T28	1293	1048	0	0
T29	1391	1215	0	0
T30	6112	5881	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	24893	0	0
T1	17464	24	0	0
T2	0	445	0	0
T3	0	34	0	0
T4	0	36	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	137390	0	0
DstReqKnown_A	212165338	210947977	0	0
SrcAckBusyChk_A	173262092	24893	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	137390	0	0
T1	17464	56	0	0
T2	0	3707	0	0
T3	0	265	0	0
T4	0	298	0	0
T5	16748	38	0	0
T6	29893	70	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	113	0	0
T23	0	49	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	57	0	0
T32	0	16	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212165338	210947977	0	0
T1	69795	69760	0	0
T5	27682	27620	0	0
T6	39573	39525	0	0
T7	2488	2474	0	0
T8	7659	7631	0	0
T26	12639	12611	0	0
T27	702	668	0	0
T28	579	524	0	0
T29	642	608	0	0
T30	3408	3346	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	24893	0	0
T1	17464	24	0	0
T2	0	445	0	0
T3	0	34	0	0
T4	0	36	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	223135	0	0
DstReqKnown_A	106082007	105473448	0	0
SrcAckBusyChk_A	173262092	24893	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	223135	0	0
T1	17464	80	0	0
T2	0	6562	0	0
T3	0	465	0	0
T4	0	520	0	0
T5	16748	55	0	0
T6	29893	100	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	210	0	0
T23	0	70	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	99	0	0
T32	0	29	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106082007	105473448	0	0
T1	34897	34880	0	0
T5	13841	13810	0	0
T6	19786	19762	0	0
T7	1243	1236	0	0
T8	3829	3815	0	0
T26	6319	6305	0	0
T27	351	334	0	0
T28	290	262	0	0
T29	321	304	0	0
T30	1704	1673	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	24893	0	0
T1	17464	24	0	0
T2	0	445	0	0
T3	0	34	0	0
T4	0	36	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	92802	0	0
DstReqKnown_A	455970422	450868654	0	0
SrcAckBusyChk_A	173262092	24893	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	92802	0	0
T1	17464	56	0	0
T2	0	2691	0	0
T3	0	159	0	0
T4	0	176	0	0
T5	16748	26	0	0
T6	29893	50	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	84	0	0
T23	0	33	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	34	0	0
T32	0	10	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455970422	450868654	0	0
T1	145536	145338	0	0
T5	57754	57542	0	0
T6	112558	112346	0	0
T7	5026	4914	0	0
T8	15982	15899	0	0
T26	26357	26274	0	0
T27	1603	1391	0	0
T28	1368	1113	0	0
T29	1448	1265	0	0
T30	6367	6126	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	24893	0	0
T1	17464	24	0	0
T2	0	445	0	0
T3	0	34	0	0
T4	0	36	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	134408	0	0
DstReqKnown_A	218693019	216258654	0	0
SrcAckBusyChk_A	173262092	24352	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	134408	0	0
T1	17464	56	0	0
T2	0	3690	0	0
T3	0	265	0	0
T4	0	219	0	0
T5	16748	40	0	0
T6	29893	70	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	116	0	0
T23	0	47	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	61	0	0
T32	0	15	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218693019	216258654	0	0
T1	69858	69763	0	0
T5	27722	27621	0	0
T6	56908	56806	0	0
T7	2413	2359	0	0
T8	7672	7632	0	0
T26	12652	12612	0	0
T27	769	668	0	0
T28	644	522	0	0
T29	694	607	0	0
T30	3055	2940	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	24352	0	0
T1	17464	24	0	0
T2	0	445	0	0
T3	0	34	0	0
T4	0	20	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	118219	0	0
DstReqKnown_A	426191130	421361137	0	0
SrcAckBusyChk_A	173262092	30961	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	118219	0	0
T1	17464	55	0	0
T2	0	2362	0	0
T3	0	163	0	0
T4	0	428	0	0
T5	16748	28	0	0
T6	29893	50	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	72	0	0
T23	0	33	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	37	0	0
T32	0	10	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426191130	421361137	0	0
T1	139710	139520	0	0
T5	55442	55239	0	0
T6	79252	79049	0	0
T7	4825	4717	0	0
T8	15342	15262	0	0
T26	25302	25222	0	0
T27	1539	1336	0	0
T28	1293	1048	0	0
T29	1391	1215	0	0
T30	6112	5881	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	30961	0	0
T1	17464	24	0	0
T2	0	456	0	0
T3	0	34	0	0
T4	0	72	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	171566	0	0
DstReqKnown_A	212165338	210947977	0	0
SrcAckBusyChk_A	173262092	30974	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	171566	0	0
T1	17464	55	0	0
T2	0	3811	0	0
T3	0	261	0	0
T4	0	604	0	0
T5	16748	38	0	0
T6	29893	70	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	115	0	0
T23	0	47	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	59	0	0
T32	0	16	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212165338	210947977	0	0
T1	69795	69760	0	0
T5	27682	27620	0	0
T6	39573	39525	0	0
T7	2488	2474	0	0
T8	7659	7631	0	0
T26	12639	12611	0	0
T27	702	668	0	0
T28	579	524	0	0
T29	642	608	0	0
T30	3408	3346	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	30974	0	0
T1	17464	24	0	0
T2	0	456	0	0
T3	0	34	0	0
T4	0	72	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	280347	0	0
DstReqKnown_A	106082007	105473448	0	0
SrcAckBusyChk_A	173262092	30933	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	280347	0	0
T1	17464	79	0	0
T2	0	6667	0	0
T3	0	454	0	0
T4	0	1065	0	0
T5	16748	54	0	0
T6	29893	100	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	206	0	0
T23	0	66	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	103	0	0
T32	0	30	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106082007	105473448	0	0
T1	34897	34880	0	0
T5	13841	13810	0	0
T6	19786	19762	0	0
T7	1243	1236	0	0
T8	3829	3815	0	0
T26	6319	6305	0	0
T27	351	334	0	0
T28	290	262	0	0
T29	321	304	0	0
T30	1704	1673	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	30933	0	0
T1	17464	24	0	0
T2	0	456	0	0
T3	0	34	0	0
T4	0	72	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	115421	0	0
DstReqKnown_A	455970422	450868654	0	0
SrcAckBusyChk_A	173262092	30956	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	115421	0	0
T1	17464	55	0	0
T2	0	2754	0	0
T3	0	158	0	0
T4	0	354	0	0
T5	16748	29	0	0
T6	29893	50	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	84	0	0
T23	0	33	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	35	0	0
T32	0	9	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455970422	450868654	0	0
T1	145536	145338	0	0
T5	57754	57542	0	0
T6	112558	112346	0	0
T7	5026	4914	0	0
T8	15982	15899	0	0
T26	26357	26274	0	0
T27	1603	1391	0	0
T28	1368	1113	0	0
T29	1448	1265	0	0
T30	6367	6126	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	30956	0	0
T1	17464	24	0	0
T2	0	456	0	0
T3	0	34	0	0
T4	0	72	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173262092	169623	0	0
DstReqKnown_A	218693019	216258654	0	0
SrcAckBusyChk_A	173262092	30577	0	0
SrcBusyKnown_A	173262092	169936041	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169623	0	0
T1	17464	55	0	0
T2	0	3786	0	0
T3	0	258	0	0
T4	0	568	0	0
T5	16748	39	0	0
T6	29893	70	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	115	0	0
T23	0	47	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	58	0	0
T32	0	15	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218693019	216258654	0	0
T1	69858	69763	0	0
T5	27722	27621	0	0
T6	56908	56806	0	0
T7	2413	2359	0	0
T8	7672	7632	0	0
T26	12652	12612	0	0
T27	769	668	0	0
T28	644	522	0	0
T29	694	607	0	0
T30	3055	2940	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	30577	0	0
T1	17464	24	0	0
T2	0	456	0	0
T3	0	34	0	0
T4	0	71	0	0
T5	16748	10	0	0
T6	29893	20	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T20	0	14	0	0
T23	0	14	0	0
T26	3689	0	0	0
T27	1588	0	0	0
T28	1364	0	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T31	0	10	0	0
T32	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173262092	169936041	0	0
T1	17464	17441	0	0
T5	16748	16687	0	0
T6	29893	29842	0	0
T7	1256	1228	0	0
T8	798	794	0	0
T26	3689	3678	0	0
T27	1588	1378	0	0
T28	1364	1111	0	0
T29	1332	1163	0	0
T30	1845	1776	0	0