Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T26
1	0	Covered	T7,T30,T38
1	1	Covered	T7,T30,T17

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	423910728	4459	0	0
g_div2.Div2Whole_A	423910728	5283	0	0
g_div4.Div4Stepped_A	211070431	4359	0	0
g_div4.Div4Whole_A	211070431	5019	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	4459	0	0
T1	139711	0	0	0
T2	0	44	0	0
T5	55442	0	0	0
T6	79252	0	0	0
T7	4826	3	0	0
T8	15343	0	0	0
T10	0	43	0	0
T26	25302	0	0	0
T27	1540	0	0	0
T28	1294	0	0	0
T29	1391	0	0	0
T30	6112	8	0	0
T38	0	6	0	0
T76	0	2	0	0
T80	0	16	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	2	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	5283	0	0
T1	139711	0	0	0
T2	0	65	0	0
T5	55442	0	0	0
T6	79252	0	0	0
T7	4826	3	0	0
T8	15343	0	0	0
T10	0	44	0	0
T17	0	1	0	0
T26	25302	0	0	0
T27	1540	0	0	0
T28	1294	0	0	0
T29	1391	0	0	0
T30	6112	7	0	0
T38	0	10	0	0
T76	0	1	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	5	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	4359	0	0
T1	69795	0	0	0
T2	0	42	0	0
T5	27682	0	0	0
T6	39573	0	0	0
T7	2488	3	0	0
T8	7659	0	0	0
T10	0	43	0	0
T26	12639	0	0	0
T27	703	0	0	0
T28	580	0	0	0
T29	642	0	0	0
T30	3408	8	0	0
T38	0	5	0	0
T76	0	2	0	0
T80	0	16	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	5019	0	0
T1	69795	0	0	0
T2	0	45	0	0
T5	27682	0	0	0
T6	39573	0	0	0
T7	2488	3	0	0
T8	7659	0	0	0
T10	0	44	0	0
T17	0	1	0	0
T26	12639	0	0	0
T27	703	0	0	0
T28	580	0	0	0
T29	642	0	0	0
T30	3408	7	0	0
T38	0	10	0	0
T76	0	1	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T26
1	0	Covered	T7,T30,T38
1	1	Covered	T7,T30,T17

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	423910728	4459	0	0
g_div2.Div2Whole_A	423910728	5283	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	4459	0	0
T1	139711	0	0	0
T2	0	44	0	0
T5	55442	0	0	0
T6	79252	0	0	0
T7	4826	3	0	0
T8	15343	0	0	0
T10	0	43	0	0
T26	25302	0	0	0
T27	1540	0	0	0
T28	1294	0	0	0
T29	1391	0	0	0
T30	6112	8	0	0
T38	0	6	0	0
T76	0	2	0	0
T80	0	16	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	2	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910728	5283	0	0
T1	139711	0	0	0
T2	0	65	0	0
T5	55442	0	0	0
T6	79252	0	0	0
T7	4826	3	0	0
T8	15343	0	0	0
T10	0	44	0	0
T17	0	1	0	0
T26	25302	0	0	0
T27	1540	0	0	0
T28	1294	0	0	0
T29	1391	0	0	0
T30	6112	7	0	0
T38	0	10	0	0
T76	0	1	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T26
1	0	Covered	T7,T30,T38
1	1	Covered	T7,T30,T17

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	211070431	4359	0	0
g_div4.Div4Whole_A	211070431	5019	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	4359	0	0
T1	69795	0	0	0
T2	0	42	0	0
T5	27682	0	0	0
T6	39573	0	0	0
T7	2488	3	0	0
T8	7659	0	0	0
T10	0	43	0	0
T26	12639	0	0	0
T27	703	0	0	0
T28	580	0	0	0
T29	642	0	0	0
T30	3408	8	0	0
T38	0	5	0	0
T76	0	2	0	0
T80	0	16	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070431	5019	0	0
T1	69795	0	0	0
T2	0	45	0	0
T5	27682	0	0	0
T6	39573	0	0	0
T7	2488	3	0	0
T8	7659	0	0	0
T10	0	44	0	0
T17	0	1	0	0
T26	12639	0	0	0
T27	703	0	0	0
T28	580	0	0	0
T29	642	0	0	0
T30	3408	7	0	0
T38	0	10	0	0
T76	0	1	0	0
T117	0	1	0	0
T118	0	9	0	0
T120	0	3	0	0