Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	516979140	455	0	0
StatusRise_A	516979140	455	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516979140	455	0	0
T1	52392	0	0	0
T6	89679	0	0	0
T17	3762	0	0	0
T18	4296	0	0	0
T19	3819	0	0	0
T20	258342	0	0	0
T21	3327	0	0	0
T25	0	12	0	0
T28	4092	3	0	0
T29	3996	0	0	0
T30	5535	0	0	0
T37	0	10	0	0
T90	0	3	0	0
T148	0	13	0	0
T160	0	9	0	0
T161	0	14	0	0
T162	0	9	0	0
T163	0	6	0	0
T164	0	16	0	0
T165	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516979140	455	0	0
T1	52392	0	0	0
T6	89679	0	0	0
T17	3762	0	0	0
T18	4296	0	0	0
T19	3819	0	0	0
T20	258342	0	0	0
T21	3327	0	0	0
T25	0	12	0	0
T28	4092	3	0	0
T29	3996	0	0	0
T30	5535	0	0	0
T37	0	10	0	0
T90	0	3	0	0
T148	0	13	0	0
T160	0	9	0	0
T161	0	14	0	0
T162	0	9	0	0
T163	0	6	0	0
T164	0	16	0	0
T165	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172326380	159	0	0
StatusRise_A	172326380	159	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	159	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	4	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	159	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	4	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172326380	145	0	0
StatusRise_A	172326380	145	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	145	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	5	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	145	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	5	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	172326380	151	0	0
StatusRise_A	172326380	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	151	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	3	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	3	0	0
T148	0	6	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172326380	151	0	0
T1	17464	0	0	0
T6	29893	0	0	0
T17	1254	0	0	0
T18	1432	0	0	0
T19	1273	0	0	0
T20	86114	0	0	0
T21	1109	0	0	0
T25	0	3	0	0
T28	1364	1	0	0
T29	1332	0	0	0
T30	1845	0	0	0
T37	0	3	0	0
T148	0	6	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	3	0	0