Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48547	0	0
CgEnOn_A	2147483647	39093	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48547	0	0
T1	1571530	3	0	0
T5	124687	3	0	0
T6	1105958	3	0	0
T7	10969	3	0	0
T8	34502	6	0	0
T17	11178	0	0	0
T18	12343	0	0	0
T19	13311	1	0	0
T20	334736	0	0	0
T21	73409	3	0	0
T25	0	29	0	0
T26	162340	9	0	0
T27	9773	11	0	0
T28	14400	12	0	0
T29	15426	23	0	0
T30	70168	3	0	0
T37	0	19	0	0
T90	0	10	0	0
T148	0	15	0	0
T160	0	15	0	0
T161	0	25	0	0
T162	0	10	0	0
T163	0	15	0	0
T164	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39093	0	0
T1	1571530	0	0	0
T2	0	237	0	0
T5	124687	0	0	0
T6	1105958	0	0	0
T8	34502	3	0	0
T17	13932	0	0	0
T18	12343	0	0	0
T19	13311	1	0	0
T20	334736	0	0	0
T21	73409	3	0	0
T22	0	6	0	0
T25	0	44	0	0
T26	162340	6	0	0
T27	9773	8	0	0
T28	14400	9	0	0
T29	15426	20	0	0
T30	70168	0	0	0
T37	0	28	0	0
T39	0	4	0	0
T40	0	4	0	0
T78	0	11	0	0
T90	0	10	0	0
T148	0	15	0	0
T160	0	15	0	0
T161	0	25	0	0
T162	0	10	0	0
T163	0	15	0	0
T164	0	30	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	211070018	149	0	0
CgEnOn_A	211070018	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070018	149	0	0
T1	69795	0	0	0
T6	39573	0	0	0
T17	582	0	0	0
T18	675	0	0	0
T19	705	0	0	0
T20	26922	0	0	0
T21	7569	0	0	0
T25	0	5	0	0
T28	579	1	0	0
T29	642	0	0	0
T30	3408	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070018	149	0	0
T1	69795	0	0	0
T6	39573	0	0	0
T17	582	0	0	0
T18	675	0	0	0
T19	705	0	0	0
T20	26922	0	0	0
T21	7569	0	0	0
T25	0	5	0	0
T28	579	1	0	0
T29	642	0	0	0
T30	3408	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105534361	149	0	0
CgEnOn_A	105534361	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105534361	149	0	0
CgEnOn_A	105534361	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105534361	149	0	0
CgEnOn_A	105534361	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	149	0	0
T1	34897	0	0	0
T6	19786	0	0	0
T17	291	0	0	0
T18	338	0	0	0
T19	353	0	0	0
T20	13461	0	0	0
T21	3785	0	0	0
T25	0	5	0	0
T28	290	1	0	0
T29	321	0	0	0
T30	1704	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423910290	149	0	0
CgEnOn_A	423910290	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910290	149	0	0
T1	139710	0	0	0
T6	79252	0	0	0
T17	1254	0	0	0
T18	1375	0	0	0
T19	1490	0	0	0
T20	53868	0	0	0
T21	15205	0	0	0
T25	0	5	0	0
T28	1293	1	0	0
T29	1391	0	0	0
T30	6112	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910290	146	0	0
T1	139710	0	0	0
T6	79252	0	0	0
T17	1254	0	0	0
T18	1375	0	0	0
T19	1490	0	0	0
T20	53868	0	0	0
T21	15205	0	0	0
T25	0	5	0	0
T28	1293	1	0	0
T29	1391	0	0	0
T30	6112	0	0	0
T37	0	3	0	0
T90	0	2	0	0
T148	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	162	0	0
CgEnOn_A	453594436	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	162	0	0
T1	145536	0	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	0	0	0
T20	86114	0	0	0
T21	15839	0	0	0
T25	0	4	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	159	0	0
T1	145536	0	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	0	0	0
T20	86114	0	0	0
T21	15839	0	0	0
T25	0	4	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	162	0	0
CgEnOn_A	453594436	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	162	0	0
T1	145536	0	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	0	0	0
T20	86114	0	0	0
T21	15839	0	0	0
T25	0	4	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	159	0	0
T1	145536	0	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	0	0	0
T20	86114	0	0	0
T21	15839	0	0	0
T25	0	4	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T90	0	1	0	0
T148	0	4	0	0
T160	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	217552577	157	0	0
CgEnOn_A	217552577	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552577	157	0	0
T1	69858	0	0	0
T6	56908	0	0	0
T15	0	1	0	0
T17	627	0	0	0
T18	687	0	0	0
T19	745	0	0	0
T20	41335	0	0	0
T21	7602	0	0	0
T25	0	3	0	0
T28	644	1	0	0
T29	694	0	0	0
T30	3055	0	0	0
T37	0	3	0	0
T148	0	6	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552577	153	0	0
T1	69858	0	0	0
T6	56908	0	0	0
T17	627	0	0	0
T18	687	0	0	0
T19	745	0	0	0
T20	41335	0	0	0
T21	7602	0	0	0
T25	0	3	0	0
T28	644	1	0	0
T29	694	0	0	0
T30	3055	0	0	0
T37	0	3	0	0
T148	0	6	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T37
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	105534361	7690	0	0
CgEnOn_A	105534361	5334	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	7690	0	0
T1	34897	1	0	0
T5	13841	1	0	0
T6	19786	1	0	0
T7	1243	1	0	0
T8	3829	2	0	0
T26	6319	1	0	0
T27	351	4	0	0
T28	290	2	0	0
T29	321	8	0	0
T30	1704	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105534361	5334	0	0
T1	34897	0	0	0
T2	0	61	0	0
T5	13841	0	0	0
T6	19786	0	0	0
T8	3829	1	0	0
T17	291	0	0	0
T25	0	5	0	0
T26	6319	0	0	0
T27	351	3	0	0
T28	290	1	0	0
T29	321	7	0	0
T30	1704	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T37
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	211070018	7714	0	0
CgEnOn_A	211070018	5358	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070018	7714	0	0
T1	69795	1	0	0
T5	27682	1	0	0
T6	39573	1	0	0
T7	2488	1	0	0
T8	7659	2	0	0
T26	12639	1	0	0
T27	702	3	0	0
T28	579	2	0	0
T29	642	7	0	0
T30	3408	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211070018	5358	0	0
T1	69795	0	0	0
T2	0	61	0	0
T5	27682	0	0	0
T6	39573	0	0	0
T8	7659	1	0	0
T17	582	0	0	0
T25	0	5	0	0
T26	12639	0	0	0
T27	702	2	0	0
T28	579	1	0	0
T29	642	6	0	0
T30	3408	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T37
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	423910290	7689	0	0
CgEnOn_A	423910290	5330	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910290	7689	0	0
T1	139710	1	0	0
T5	55442	1	0	0
T6	79252	1	0	0
T7	4825	1	0	0
T8	15342	2	0	0
T26	25302	1	0	0
T27	1539	4	0	0
T28	1293	2	0	0
T29	1391	8	0	0
T30	6112	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423910290	5330	0	0
T1	139710	0	0	0
T2	0	54	0	0
T5	55442	0	0	0
T6	79252	0	0	0
T8	15342	1	0	0
T17	1254	0	0	0
T25	0	5	0	0
T26	25302	0	0	0
T27	1539	3	0	0
T28	1293	1	0	0
T29	1391	7	0	0
T30	6112	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T37
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	217552577	7675	0	0
CgEnOn_A	217552577	5317	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552577	7675	0	0
T1	69858	1	0	0
T5	27722	1	0	0
T6	56908	1	0	0
T7	2413	1	0	0
T8	7672	2	0	0
T26	12652	1	0	0
T27	769	4	0	0
T28	644	2	0	0
T29	694	7	0	0
T30	3055	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217552577	5317	0	0
T1	69858	0	0	0
T2	0	57	0	0
T5	27722	0	0	0
T6	56908	0	0	0
T8	7672	1	0	0
T17	627	0	0	0
T25	0	3	0	0
T26	12652	0	0	0
T27	769	3	0	0
T28	644	1	0	0
T29	694	6	0	0
T30	3055	0	0	0
T37	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T78	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Covered	T26,T19,T21
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	4158	0	0
CgEnOn_A	453594436	4155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4158	0	0
T1	145536	0	0	0
T2	0	61	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	3	0	0
T22	0	6	0	0
T25	0	4	0	0
T26	26357	6	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4155	0	0
T1	145536	0	0	0
T2	0	61	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	3	0	0
T22	0	6	0	0
T25	0	4	0	0
T26	26357	6	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Covered	T26,T19,T21
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	4132	0	0
CgEnOn_A	453594436	4129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4132	0	0
T1	145536	0	0	0
T2	0	65	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	2	0	0
T21	0	4	0	0
T22	0	4	0	0
T25	0	4	0	0
T26	26357	5	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4129	0	0
T1	145536	0	0	0
T2	0	65	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	2	0	0
T21	0	4	0	0
T22	0	4	0	0
T25	0	4	0	0
T26	26357	5	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Covered	T26,T19,T21
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	4114	0	0
CgEnOn_A	453594436	4111	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4114	0	0
T1	145536	0	0	0
T2	0	52	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	2	0	0
T22	0	6	0	0
T25	0	4	0	0
T26	26357	7	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4111	0	0
T1	145536	0	0	0
T2	0	52	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	2	0	0
T22	0	6	0	0
T25	0	4	0	0
T26	26357	7	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T2
1	0	Covered	T26,T19,T21
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	453594436	4149	0	0
CgEnOn_A	453594436	4146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4149	0	0
T1	145536	0	0	0
T2	0	69	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	3	0	0
T22	0	7	0	0
T25	0	4	0	0
T26	26357	14	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453594436	4146	0	0
T1	145536	0	0	0
T2	0	69	0	0
T6	112558	0	0	0
T17	1307	0	0	0
T18	1432	0	0	0
T19	1552	1	0	0
T21	0	3	0	0
T22	0	7	0	0
T25	0	4	0	0
T26	26357	14	0	0
T27	1603	0	0	0
T28	1368	1	0	0
T29	1448	0	0	0
T30	6367	0	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0