Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	653549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3895365

1

T7

8

T8

34

T9

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1115998	1			T7	9		T8	56		T9	6
values[0x0]	1577331	1			T7	9		T8	19		T9	5
values[0x1]	1855585	1			T7	10		T8	23		T9	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4191136

1

T7

11

T8

42

T9

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17671	1			T26	40		T4	3		T6	3
valid_sources[0x01]	19003	1			T8	3		T4	2		T6	5
valid_sources[0x02]	17084	1			T4	3		T6	1		T1	34
valid_sources[0x03]	17256	1			T50	1		T6	1		T3	254
valid_sources[0x04]	16799	1			T4	2		T3	305		T38	1
valid_sources[0x05]	17459	1			T4	3		T6	1		T46	2
valid_sources[0x06]	18594	1			T52	2		T4	5		T41	1
valid_sources[0x07]	17885	1			T8	7		T50	1		T4	1
valid_sources[0x08]	18022	1			T9	5		T50	1		T4	1
valid_sources[0x09]	18531	1			T4	2		T41	3		T3	288
valid_sources[0x0a]	17819	1			T4	1		T6	1		T1	49
valid_sources[0x0b]	18776	1			T50	1		T40	5		T6	1
valid_sources[0x0c]	17071	1			T4	1		T6	4		T1	36
valid_sources[0x0d]	17002	1			T50	1		T4	4		T6	1
valid_sources[0x0e]	16409	1			T4	4		T20	1		T3	328
valid_sources[0x0f]	15608	1			T4	8		T6	3		T1	44
valid_sources[0x10]	16803	1			T8	3		T6	3		T3	219
valid_sources[0x11]	17299	1			T4	1		T6	3		T3	348
valid_sources[0x12]	18369	1			T1	6		T3	213		T45	1
valid_sources[0x13]	16512	1			T50	1		T4	1		T3	213
valid_sources[0x14]	19608	1			T52	2		T4	1		T6	1
valid_sources[0x15]	18010	1			T8	8		T4	3		T3	337
valid_sources[0x16]	18501	1			T8	1		T4	1		T6	1
valid_sources[0x17]	17283	1			T50	1		T19	1		T3	317
valid_sources[0x18]	16784	1			T25	1		T4	1		T6	1
valid_sources[0x19]	19027	1			T7	1		T50	1		T4	1
valid_sources[0x1a]	17322	1			T4	4		T6	6		T41	1
valid_sources[0x1b]	17258	1			T50	1		T4	3		T6	4
valid_sources[0x1c]	17105	1			T4	1		T6	3		T1	16
valid_sources[0x1d]	17917	1			T4	9		T3	250		T84	1
valid_sources[0x1e]	18319	1			T9	8		T6	3		T1	17
valid_sources[0x1f]	17175	1			T4	1		T6	2		T19	1
valid_sources[0x20]	17989	1			T7	1		T50	1		T4	4
valid_sources[0x21]	16979	1			T4	2		T41	1		T3	251
valid_sources[0x22]	17021	1			T8	6		T4	5		T6	1
valid_sources[0x23]	17585	1			T52	2		T50	1		T4	1
valid_sources[0x24]	16981	1			T52	1		T4	2		T6	2
valid_sources[0x25]	17282	1			T8	3		T52	2		T4	2
valid_sources[0x26]	17185	1			T7	1		T4	2		T1	101
valid_sources[0x27]	16228	1			T52	1		T4	2		T6	2
valid_sources[0x28]	18547	1			T4	2		T42	1		T20	1
valid_sources[0x29]	19246	1			T4	1		T6	3		T42	1
valid_sources[0x2a]	17795	1			T6	3		T19	1		T3	375
valid_sources[0x2b]	19324	1			T4	2		T6	4		T1	60
valid_sources[0x2c]	18058	1			T4	1		T6	2		T19	1
valid_sources[0x2d]	17509	1			T28	2		T4	1		T42	1
valid_sources[0x2e]	18130	1			T7	1		T4	2		T21	1
valid_sources[0x2f]	18178	1			T50	1		T4	1		T3	248
valid_sources[0x30]	17445	1			T4	2		T6	3		T3	253
valid_sources[0x31]	17261	1			T40	12		T6	1		T3	247
valid_sources[0x32]	17709	1			T50	1		T4	2		T6	4
valid_sources[0x33]	18260	1			T7	2		T4	2		T6	2
valid_sources[0x34]	17221	1			T7	1		T52	2		T6	1
valid_sources[0x35]	18148	1			T52	1		T4	1		T6	4
valid_sources[0x36]	18649	1			T8	1		T4	3		T6	2
valid_sources[0x37]	17255	1			T4	2		T20	1		T3	355
valid_sources[0x38]	18441	1			T50	1		T4	4		T6	3
valid_sources[0x39]	17321	1			T6	1		T1	34		T3	297
valid_sources[0x3a]	17748	1			T50	1		T6	3		T3	318
valid_sources[0x3b]	17661	1			T4	4		T3	254		T140	1
valid_sources[0x3c]	18001	1			T4	4		T6	2		T20	1
valid_sources[0x3d]	16551	1			T52	1		T4	1		T6	1
valid_sources[0x3e]	17808	1			T4	1		T20	1		T24	5
valid_sources[0x3f]	18892	1			T4	2		T6	2		T3	211
valid_sources[0x40]	16804	1			T4	5		T6	1		T20	1
valid_sources[0x41]	18249	1			T6	1		T41	1		T3	209
valid_sources[0x42]	16675	1			T29	81		T6	4		T41	1
valid_sources[0x43]	16352	1			T8	3		T4	1		T43	1
valid_sources[0x44]	18460	1			T8	2		T50	1		T6	6
valid_sources[0x45]	18652	1			T6	1		T20	2		T3	323
valid_sources[0x46]	16232	1			T8	2		T52	3		T4	5
valid_sources[0x47]	18911	1			T4	2		T6	5		T20	1
valid_sources[0x48]	18199	1			T4	3		T20	1		T3	296
valid_sources[0x49]	18045	1			T7	1		T25	1		T50	1
valid_sources[0x4a]	17824	1			T6	1		T20	1		T3	310
valid_sources[0x4b]	17879	1			T1	47		T20	1		T3	325
valid_sources[0x4c]	17434	1			T8	1		T4	3		T42	2
valid_sources[0x4d]	17518	1			T50	1		T6	2		T19	1
valid_sources[0x4e]	19352	1			T50	1		T4	1		T42	2
valid_sources[0x4f]	19016	1			T4	3		T46	2		T19	2
valid_sources[0x50]	17338	1			T8	2		T4	1		T6	3
valid_sources[0x51]	17798	1			T4	3		T6	2		T1	41
valid_sources[0x52]	17211	1			T25	1		T50	1		T4	1
valid_sources[0x53]	18559	1			T52	3		T6	2		T20	2
valid_sources[0x54]	16830	1			T50	1		T4	1		T6	4
valid_sources[0x55]	18867	1			T52	1		T4	1		T6	1
valid_sources[0x56]	17596	1			T8	3		T28	1		T31	5
valid_sources[0x57]	18047	1			T6	1		T24	5		T3	335
valid_sources[0x58]	17923	1			T7	1		T4	2		T6	1
valid_sources[0x59]	17224	1			T52	1		T4	1		T41	1
valid_sources[0x5a]	18096	1			T4	5		T24	4		T3	228
valid_sources[0x5b]	18593	1			T50	1		T6	2		T41	1
valid_sources[0x5c]	17547	1			T7	1		T6	2		T1	67
valid_sources[0x5d]	18029	1			T4	2		T6	2		T3	216
valid_sources[0x5e]	17314	1			T52	3		T4	3		T6	1
valid_sources[0x5f]	18412	1			T4	1		T6	5		T41	2
valid_sources[0x60]	17454	1			T4	4		T6	1		T3	232
valid_sources[0x61]	19876	1			T4	1		T2	1582		T3	373
valid_sources[0x62]	18173	1			T50	1		T4	2		T6	3
valid_sources[0x63]	18975	1			T6	3		T3	236		T83	1
valid_sources[0x64]	17595	1			T7	1		T4	1		T6	1
valid_sources[0x65]	17415	1			T8	3		T4	2		T6	1
valid_sources[0x66]	17503	1			T52	1		T4	1		T6	3
valid_sources[0x67]	18715	1			T4	4		T6	1		T3	259
valid_sources[0x68]	18106	1			T52	1		T4	1		T6	2
valid_sources[0x69]	18527	1			T6	2		T20	1		T3	269
valid_sources[0x6a]	17641	1			T7	1		T4	2		T6	1
valid_sources[0x6b]	19036	1			T52	1		T6	2		T43	3
valid_sources[0x6c]	19927	1			T52	2		T4	4		T3	324
valid_sources[0x6d]	16936	1			T3	353		T36	1		T174	1
valid_sources[0x6e]	17958	1			T50	1		T6	2		T3	403
valid_sources[0x6f]	17696	1			T4	1		T5	235		T1	36
valid_sources[0x70]	18984	1			T8	1		T6	1		T3	222
valid_sources[0x71]	18141	1			T6	1		T3	266		T84	1
valid_sources[0x72]	18316	1			T7	1		T8	5		T6	1
valid_sources[0x73]	18787	1			T4	1		T6	4		T20	2
valid_sources[0x74]	18118	1			T7	1		T3	294		T45	1
valid_sources[0x75]	18307	1			T4	2		T6	2		T41	1
valid_sources[0x76]	17960	1			T6	4		T42	1		T1	3
valid_sources[0x77]	18387	1			T6	1		T1	7		T3	197
valid_sources[0x78]	18025	1			T7	1		T6	3		T20	1
valid_sources[0x79]	16819	1			T50	1		T1	4		T20	1
valid_sources[0x7a]	17750	1			T4	1		T6	5		T3	150
valid_sources[0x7b]	19937	1			T4	3		T6	3		T1	21
valid_sources[0x7c]	18071	1			T8	3		T50	2		T4	1
valid_sources[0x7d]	18079	1			T50	1		T6	3		T3	326
valid_sources[0x7e]	17003	1			T6	2		T1	2		T3	404
valid_sources[0x7f]	17652	1			T50	1		T41	1		T42	2
valid_sources[0x80]	16814	1			T8	1		T52	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

982667

1

T7

4

T8

23

T9

4

values[0x0]

all_enables

biggest_size

1479014

1

T7

3

T8

8

T9

2

values[0x1]

all_enables

biggest_size

1433684

1

T7

1

T8

3

T9

2