Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T4
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T30,T44,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1167955683	15482	0	0
GateOpen_A	1167955683	21644	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1167955683	15482	0	0
T1	0	29	0	0
T2	0	144	0	0
T3	0	138	0	0
T4	96993	0	0	0
T5	44791	0	0	0
T6	375595	0	0	0
T12	0	24	0	0
T20	0	4	0	0
T21	0	18	0	0
T29	38852	4	0	0
T30	6143	6	0	0
T31	10427	0	0	0
T40	3751	0	0	0
T41	8572	4	0	0
T44	0	6	0	0
T50	5511	0	0	0
T52	7591	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1167955683	21644	0	0
T4	0	40	0	0
T7	5090	4	0	0
T8	5385	0	0	0
T9	14826	4	0	0
T25	5091	0	0	0
T26	4943	0	0	0
T27	6760	0	0	0
T28	3221	4	0	0
T29	38852	4	0	0
T30	6143	10	0	0
T31	10427	4	0	0
T40	0	4	0	0
T50	0	4	0	0
T52	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T4
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T30,T44,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	128989500	3709	0	0
GateOpen_A	128989500	5247	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989500	3709	0	0
T1	0	7	0	0
T2	0	33	0	0
T3	0	34	0	0
T4	7087	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T12	0	6	0	0
T20	0	1	0	0
T21	0	3	0	0
T29	4290	1	0	0
T30	674	1	0	0
T31	1155	0	0	0
T40	428	0	0	0
T41	937	1	0	0
T44	0	1	0	0
T50	590	0	0	0
T52	907	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989500	5247	0	0
T4	0	10	0	0
T7	579	1	0	0
T8	576	0	0	0
T9	1695	1	0	0
T25	578	0	0	0
T26	566	0	0	0
T27	820	0	0	0
T28	346	1	0	0
T29	4290	1	0	0
T30	674	2	0	0
T31	1155	1	0	0
T40	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T4
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T30,T44,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	257979881	3924	0	0
GateOpen_A	257979881	5462	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979881	3924	0	0
T1	0	7	0	0
T2	0	37	0	0
T3	0	35	0	0
T4	14180	0	0	0
T5	5594	0	0	0
T6	75776	0	0	0
T12	0	6	0	0
T20	0	1	0	0
T21	0	5	0	0
T29	8580	1	0	0
T30	1348	1	0	0
T31	2309	0	0	0
T40	856	0	0	0
T41	1874	1	0	0
T44	0	1	0	0
T50	1180	0	0	0
T52	1814	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979881	5462	0	0
T4	0	10	0	0
T7	1157	1	0	0
T8	1152	0	0	0
T9	3390	1	0	0
T25	1155	0	0	0
T26	1134	0	0	0
T27	1645	0	0	0
T28	691	1	0	0
T29	8580	1	0	0
T30	1348	2	0	0
T31	2309	1	0	0
T40	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T4
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T30,T44,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	517265177	3926	0	0
GateOpen_A	517265177	5469	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517265177	3926	0	0
T1	0	6	0	0
T2	0	37	0	0
T3	0	35	0	0
T4	50483	0	0	0
T5	24266	0	0	0
T6	151577	0	0	0
T12	0	6	0	0
T20	0	1	0	0
T21	0	5	0	0
T29	17321	1	0	0
T30	2817	1	0	0
T31	4642	0	0	0
T40	1644	0	0	0
T41	3840	1	0	0
T44	0	1	0	0
T50	2494	0	0	0
T52	3246	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517265177	5469	0	0
T4	0	10	0	0
T7	2236	1	0	0
T8	2438	0	0	0
T9	6494	1	0	0
T25	2239	0	0	0
T26	2162	0	0	0
T27	2863	0	0	0
T28	1456	1	0	0
T29	17321	1	0	0
T30	2817	2	0	0
T31	4642	1	0	0
T40	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T4
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T30,T44,T51
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	263721125	3923	0	0
GateOpen_A	263721125	5466	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263721125	3923	0	0
T1	0	9	0	0
T2	0	37	0	0
T3	0	34	0	0
T4	25243	0	0	0
T5	12133	0	0	0
T6	110354	0	0	0
T12	0	6	0	0
T20	0	1	0	0
T21	0	5	0	0
T29	8661	1	0	0
T30	1304	3	0	0
T31	2321	0	0	0
T40	823	0	0	0
T41	1921	1	0	0
T44	0	3	0	0
T50	1247	0	0	0
T52	1624	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263721125	5466	0	0
T4	0	10	0	0
T7	1118	1	0	0
T8	1219	0	0	0
T9	3247	1	0	0
T25	1119	0	0	0
T26	1081	0	0	0
T27	1432	0	0	0
T28	728	1	0	0
T29	8661	1	0	0
T30	1304	4	0	0
T31	2321	1	0	0
T40	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0