Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	875000530	81362	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875000530	81362	0	0
T1	2734780	394	0	0
T2	2252355	623	0	0
T3	981145	974	0	0
T12	510780	818	0	0
T13	0	401	0	0
T14	0	375	0	0
T15	0	273	0	0
T16	0	183	0	0
T17	0	94	0	0
T18	0	89	0	0
T19	7365	0	0	0
T20	10885	0	0	0
T21	3880	0	0	0
T22	12310	0	0	0
T23	12790	0	0	0
T24	9400	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	175000106	12009	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	12009	0	0
T1	546956	53	0	0
T2	450471	83	0	0
T3	196229	179	0	0
T12	102156	107	0	0
T13	0	59	0	0
T14	0	55	0	0
T15	0	40	0	0
T16	0	29	0	0
T17	0	15	0	0
T18	0	14	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T22	2462	0	0	0
T23	2558	0	0	0
T24	1880	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	175000106	11793	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	11793	0	0
T1	546956	51	0	0
T2	450471	82	0	0
T3	196229	179	0	0
T12	102156	103	0	0
T13	0	50	0	0
T14	0	45	0	0
T15	0	40	0	0
T16	0	30	0	0
T17	0	15	0	0
T18	0	14	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T22	2462	0	0	0
T23	2558	0	0	0
T24	1880	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	175000106	16462	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	16462	0	0
T1	546956	82	0	0
T2	450471	124	0	0
T3	196229	189	0	0
T12	102156	169	0	0
T13	0	79	0	0
T14	0	74	0	0
T15	0	54	0	0
T16	0	38	0	0
T17	0	19	0	0
T18	0	18	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T22	2462	0	0	0
T23	2558	0	0	0
T24	1880	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	175000106	16374	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	16374	0	0
T1	546956	80	0	0
T2	450471	125	0	0
T3	196229	192	0	0
T12	102156	169	0	0
T13	0	81	0	0
T14	0	79	0	0
T15	0	55	0	0
T16	0	38	0	0
T17	0	19	0	0
T18	0	18	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T22	2462	0	0	0
T23	2558	0	0	0
T24	1880	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	175000106	24724	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	24724	0	0
T1	546956	128	0	0
T2	450471	209	0	0
T3	196229	235	0	0
T12	102156	270	0	0
T13	0	132	0	0
T14	0	122	0	0
T15	0	84	0	0
T16	0	48	0	0
T17	0	26	0	0
T18	0	25	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T22	2462	0	0	0
T23	2558	0	0	0
T24	1880	0	0	0