Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T29,T4,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	175000106	172700939	0	0
AllClkBypReqTrue_A	175000106	142860	0	0
IoClkBypReqFalse_A	175000106	172622587	0	2415
IoClkBypReqTrue_A	175000106	216750	0	0
LcClkBypAckFalse_A	175000106	172715131	0	0
LcClkBypAckTrue_A	175000106	128668	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	172700939	0	0
T7	1676	1553	0	0
T8	2489	2281	0	0
T9	1014	890	0	0
T25	1119	942	0	0
T26	2229	2104	0	0
T27	2981	2278	0	0
T28	1501	1277	0	0
T29	2346	2289	0	0
T30	1099	999	0	0
T31	1208	1169	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	142860	0	0
T1	0	752	0	0
T2	0	69	0	0
T7	1676	32	0	0
T8	2489	0	0	0
T9	1014	98	0	0
T19	0	42	0	0
T22	0	403	0	0
T25	1119	55	0	0
T26	2229	0	0	0
T27	2981	519	0	0
T28	1501	0	0	0
T29	2346	0	0	0
T30	1099	0	0	0
T31	1208	0	0	0
T40	0	65	0	0
T52	0	99	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	172622587	0	2415
T7	1676	1446	0	3
T8	2489	2279	0	3
T9	1014	923	0	3
T25	1119	910	0	3
T26	2229	1800	0	3
T27	2981	2049	0	3
T28	1501	1240	0	3
T29	2346	2285	0	3
T30	1099	997	0	3
T31	1208	1167	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	216750	0	0
T1	0	1333	0	0
T7	1676	137	0	0
T8	2489	0	0	0
T9	1014	63	0	0
T19	0	162	0	0
T25	1119	85	0	0
T26	2229	302	0	0
T27	2981	746	0	0
T28	1501	35	0	0
T29	2346	0	0	0
T30	1099	0	0	0
T31	1208	0	0	0
T40	0	155	0	0
T52	0	34	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	172715131	0	0
T7	1676	1486	0	0
T8	2489	2281	0	0
T9	1014	933	0	0
T25	1119	947	0	0
T26	2229	1919	0	0
T27	2981	2340	0	0
T28	1501	1271	0	0
T29	2346	2289	0	0
T30	1099	999	0	0
T31	1208	1169	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	128668	0	0
T1	0	890	0	0
T7	1676	99	0	0
T8	2489	0	0	0
T9	1014	55	0	0
T19	0	92	0	0
T25	1119	50	0	0
T26	2229	185	0	0
T27	2981	457	0	0
T28	1501	6	0	0
T29	2346	0	0	0
T30	1099	0	0	0
T31	1208	0	0	0
T40	0	99	0	0
T52	0	30	0	0