Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16215	0	0
TransStop_A	2147483647	8213	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16215	0	0
T1	0	38	0	0
T2	0	108	0	0
T8	10160	32	0	0
T9	27056	0	0	0
T20	0	4	0	0
T23	0	42	0	0
T25	9328	0	0	0
T26	9008	0	0	0
T27	11928	0	0	0
T28	6064	0	0	0
T29	72172	4	0	0
T30	10888	0	0	0
T31	19344	0	0	0
T41	0	4	0	0
T42	0	7	0	0
T46	0	19	0	0
T50	0	19	0	0
T52	13524	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8213	0	0
T1	0	11	0	0
T2	0	70	0	0
T3	0	75	0	0
T8	10160	16	0	0
T9	27056	0	0	0
T20	0	4	0	0
T23	0	19	0	0
T25	9328	0	0	0
T26	9008	0	0	0
T27	11928	0	0	0
T28	6064	0	0	0
T29	72172	4	0	0
T30	10888	0	0	0
T31	19344	0	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	0	9	0	0
T50	0	11	0	0
T52	13524	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549846352	4018	0	0
TransStop_A	549846352	2008	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	4018	0	0
T1	0	12	0	0
T2	0	29	0	0
T8	2540	9	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	13	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	5	0	0
T50	0	5	0	0
T52	3381	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	2008	0	0
T1	0	5	0	0
T2	0	21	0	0
T3	0	38	0	0
T8	2540	4	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	6	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T46	0	3	0	0
T50	0	3	0	0
T52	3381	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549846352	4136	0	0
TransStop_A	549846352	2075	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	4136	0	0
T1	0	11	0	0
T2	0	25	0	0
T8	2540	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	11	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	3	0	0
T50	0	5	0	0
T52	3381	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	2075	0	0
T1	0	2	0	0
T2	0	16	0	0
T3	0	37	0	0
T8	2540	3	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	4	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T46	0	1	0	0
T50	0	3	0	0
T52	3381	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549846352	4027	0	0
TransStop_A	549846352	2065	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	4027	0	0
T1	0	7	0	0
T2	0	27	0	0
T8	2540	7	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	11	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	6	0	0
T50	0	5	0	0
T52	3381	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	2065	0	0
T1	0	3	0	0
T2	0	17	0	0
T8	2540	4	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	6	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	3	0	0
T50	0	3	0	0
T52	3381	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	549846352	4034	0	0
TransStop_A	549846352	2065	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	4034	0	0
T1	0	8	0	0
T2	0	27	0	0
T8	2540	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	7	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T46	0	5	0	0
T50	0	4	0	0
T52	3381	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549846352	2065	0	0
T1	0	1	0	0
T2	0	16	0	0
T8	2540	5	0	0
T9	6764	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	2332	0	0	0
T26	2252	0	0	0
T27	2982	0	0	0
T28	1516	0	0	0
T29	18043	1	0	0
T30	2722	0	0	0
T31	4836	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	2	0	0
T50	0	2	0	0
T52	3381	0	0	0