Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	175939177	5677904	0	0
clk_enables_rd_A	175939177	74246	0	0
clk_hints_rd_A	175939177	65538	0	0
extclk_ctrl_rd_A	175939177	79376	0	0
extclk_ctrl_regwen_rd_A	175939177	62738	0	0
jitter_enable_rd_A	175939177	85390	0	0
jitter_regwen_rd_A	175939177	70259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	5677904	0	0
T3	196229	91373	0	0
T12	102156	0	0	0
T33	0	91754	0	0
T35	1615	0	0	0
T36	50878	0	0	0
T45	1426	0	0	0
T48	0	210186	0	0
T53	0	205352	0	0
T76	0	136710	0	0
T77	0	69563	0	0
T78	0	132740	0	0
T79	0	84824	0	0
T80	0	36948	0	0
T81	0	128526	0	0
T82	1680	0	0	0
T83	2431	0	0	0
T84	1980	0	0	0
T85	2131	0	0	0
T86	2618	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	74246	0	0
T1	546956	0	0	0
T2	450471	0	0	0
T12	0	27	0	0
T15	0	7	0	0
T19	1473	0	0	0
T20	2177	0	0	0
T21	776	0	0	0
T33	0	3598	0	0
T41	1999	8	0	0
T42	1654	0	0	0
T43	1268	0	0	0
T44	1188	0	0	0
T46	1626	0	0	0
T77	0	2938	0	0
T79	0	2009	0	0
T80	0	773	0	0
T137	0	2	0	0
T138	0	1	0	0
T139	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	65538	0	0
T1	546956	0	0	0
T2	450471	0	0	0
T12	0	19	0	0
T15	0	4	0	0
T19	1473	0	0	0
T20	2177	8	0	0
T21	776	0	0	0
T33	0	2924	0	0
T41	1999	1	0	0
T42	1654	0	0	0
T43	1268	0	0	0
T44	1188	0	0	0
T46	1626	0	0	0
T77	0	2536	0	0
T79	0	1665	0	0
T80	0	560	0	0
T138	0	5	0	0
T139	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	79376	0	0
T1	0	95	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T12	0	38	0	0
T15	0	45	0	0
T27	2981	71	0	0
T28	1501	0	0	0
T29	2346	0	0	0
T30	1099	0	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T50	2493	0	0	0
T52	1690	0	0	0
T85	0	41	0	0
T86	0	61	0	0
T88	0	65	0	0
T140	0	54	0	0
T141	0	83	0	0
T142	0	24	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	62738	0	0
T33	317708	3083	0	0
T34	19520	0	0	0
T77	0	2486	0	0
T79	0	1448	0	0
T80	0	629	0	0
T99	2037	0	0	0
T139	2218	0	0	0
T143	0	16	0	0
T144	0	22	0	0
T145	0	12	0	0
T146	0	14	0	0
T147	0	32	0	0
T148	0	4	0	0
T149	1048	0	0	0
T150	2105	0	0	0
T151	1497	0	0	0
T152	1403	0	0	0
T153	1629	0	0	0
T154	13146	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	85390	0	0
T1	546956	0	0	0
T2	450471	0	0	0
T12	0	853	0	0
T15	0	107	0	0
T19	1473	0	0	0
T20	2177	65	0	0
T21	776	0	0	0
T33	0	3912	0	0
T41	1999	80	0	0
T42	1654	0	0	0
T43	1268	0	0	0
T44	1188	0	0	0
T46	1626	0	0	0
T77	0	3163	0	0
T137	0	76	0	0
T138	0	94	0	0
T139	0	125	0	0
T155	0	42	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175939177	70259	0	0
T33	317708	3471	0	0
T34	19520	0	0	0
T49	0	4635	0	0
T77	0	2760	0	0
T79	0	1898	0	0
T80	0	705	0	0
T99	2037	0	0	0
T139	2218	0	0	0
T149	1048	0	0	0
T150	2105	0	0	0
T151	1497	0	0	0
T152	1403	0	0	0
T153	1629	0	0	0
T154	13146	0	0	0
T156	0	4790	0	0
T157	0	844	0	0
T158	0	5277	0	0
T159	0	2771	0	0
T160	0	1105	0	0