Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	525000318	443	0	0
StatusRise_A	525000318	443	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525000318	443	0	0
T4	118326	0	0	0
T5	73560	0	0	0
T6	624090	0	0	0
T30	3297	7	0	0
T31	3624	0	0	0
T40	4929	0	0	0
T41	5997	0	0	0
T42	4962	0	0	0
T44	0	5	0	0
T50	7479	0	0	0
T51	0	15	0	0
T52	5070	0	0	0
T60	0	15	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	10	0	0
T164	0	12	0	0
T165	0	6	0	0
T166	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525000318	443	0	0
T4	118326	0	0	0
T5	73560	0	0	0
T6	624090	0	0	0
T30	3297	7	0	0
T31	3624	0	0	0
T40	4929	0	0	0
T41	5997	0	0	0
T42	4962	0	0	0
T44	0	5	0	0
T50	7479	0	0	0
T51	0	15	0	0
T52	5070	0	0	0
T60	0	15	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	10	0	0
T164	0	12	0	0
T165	0	6	0	0
T166	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	175000106	135	0	0
StatusRise_A	175000106	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	135	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	3	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	4	0	0
T52	1690	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	135	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	3	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	4	0	0
T52	1690	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	175000106	154	0	0
StatusRise_A	175000106	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	154	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	1	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	7	0	0
T52	1690	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	154	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	1	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	7	0	0
T52	1690	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	175000106	154	0	0
StatusRise_A	175000106	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	154	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	3	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	3	0	0
T50	2493	0	0	0
T51	0	4	0	0
T52	1690	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175000106	154	0	0
T4	39442	0	0	0
T5	24520	0	0	0
T6	208030	0	0	0
T30	1099	3	0	0
T31	1208	0	0	0
T40	1643	0	0	0
T41	1999	0	0	0
T42	1654	0	0	0
T44	0	3	0	0
T50	2493	0	0	0
T51	0	4	0	0
T52	1690	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0