Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51218	0	0
CgEnOn_A	2147483647	42296	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51218	0	0
T4	216338	0	0	0
T5	100939	0	0	0
T6	899165	0	0	0
T7	5088	3	0	0
T8	15541	12	0	0
T9	41879	3	0	0
T25	14413	3	0	0
T26	13950	3	0	0
T27	18681	3	0	0
T28	9283	3	0	0
T29	111018	10	0	0
T30	29956	14	0	0
T31	52168	3	0	0
T40	8029	0	0	0
T41	18445	1	0	0
T42	7865	0	0	0
T44	0	6	0	0
T50	11882	5	0	0
T51	0	35	0	0
T52	29686	0	0	0
T60	0	35	0	0
T161	0	10	0	0
T162	0	10	0	0
T163	0	20	0	0
T164	0	20	0	0
T165	0	10	0	0
T166	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42296	0	0
T1	0	57	0	0
T2	0	162	0	0
T3	0	188	0	0
T4	313328	0	0	0
T5	145728	0	0	0
T6	1274758	0	0	0
T8	10156	9	0	0
T9	27056	0	0	0
T12	0	21	0	0
T20	0	4	0	0
T21	0	19	0	0
T25	9324	0	0	0
T26	9008	0	0	0
T27	11924	0	0	0
T28	6064	0	0	0
T29	111018	4	0	0
T30	29956	11	0	0
T31	52168	0	0	0
T40	11778	0	0	0
T41	27016	4	0	0
T42	7865	1	0	0
T44	0	9	0	0
T50	17390	5	0	0
T51	0	35	0	0
T52	37274	0	0	0
T60	0	35	0	0
T161	0	10	0	0
T162	0	10	0	0
T163	0	20	0	0
T164	0	20	0	0
T165	0	10	0	0
T166	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	257979464	164	0	0
CgEnOn_A	257979464	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979464	164	0	0
T4	14179	0	0	0
T5	5593	0	0	0
T6	75776	0	0	0
T30	1348	1	0	0
T31	2309	0	0	0
T40	856	0	0	0
T41	1874	0	0	0
T42	799	0	0	0
T44	0	1	0	0
T50	1179	0	0	0
T51	0	7	0	0
T52	1813	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979464	164	0	0
T4	14179	0	0	0
T5	5593	0	0	0
T6	75776	0	0	0
T30	1348	1	0	0
T31	2309	0	0	0
T40	856	0	0	0
T41	1874	0	0	0
T42	799	0	0	0
T44	0	1	0	0
T50	1179	0	0	0
T51	0	7	0	0
T52	1813	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	128989085	164	0	0
CgEnOn_A	128989085	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	128989085	164	0	0
CgEnOn_A	128989085	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	128989085	164	0	0
CgEnOn_A	128989085	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	164	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	0	0	0
T42	400	0	0	0
T44	0	1	0	0
T50	590	0	0	0
T51	0	7	0	0
T52	906	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	517264723	164	0	0
CgEnOn_A	517264723	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517264723	164	0	0
T4	50483	0	0	0
T5	24265	0	0	0
T6	151576	0	0	0
T30	2816	1	0	0
T31	4642	0	0	0
T40	1643	0	0	0
T41	3840	0	0	0
T42	1636	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	7	0	0
T52	3246	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517264723	154	0	0
T4	50483	0	0	0
T5	24265	0	0	0
T6	151576	0	0	0
T30	2816	1	0	0
T31	4642	0	0	0
T40	1643	0	0	0
T41	3840	0	0	0
T42	1636	0	0	0
T44	0	1	0	0
T50	2493	0	0	0
T51	0	7	0	0
T52	3246	0	0	0
T60	0	7	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	136	0	0
CgEnOn_A	549845917	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	136	0	0
T4	52588	0	0	0
T5	25277	0	0	0
T6	223898	0	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T40	1712	0	0	0
T41	4000	0	0	0
T42	1706	0	0	0
T44	0	1	0	0
T50	2597	0	0	0
T51	0	4	0	0
T52	3381	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	135	0	0
T4	52588	0	0	0
T5	25277	0	0	0
T6	223898	0	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T40	1712	0	0	0
T41	4000	0	0	0
T42	1706	0	0	0
T44	0	1	0	0
T50	2597	0	0	0
T51	0	4	0	0
T52	3381	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	136	0	0
CgEnOn_A	549845917	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	136	0	0
T4	52588	0	0	0
T5	25277	0	0	0
T6	223898	0	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T40	1712	0	0	0
T41	4000	0	0	0
T42	1706	0	0	0
T44	0	1	0	0
T50	2597	0	0	0
T51	0	4	0	0
T52	3381	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	135	0	0
T4	52588	0	0	0
T5	25277	0	0	0
T6	223898	0	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T40	1712	0	0	0
T41	4000	0	0	0
T42	1706	0	0	0
T44	0	1	0	0
T50	2597	0	0	0
T51	0	4	0	0
T52	3381	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	263720705	156	0	0
CgEnOn_A	263720705	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263720705	156	0	0
T4	25242	0	0	0
T5	12133	0	0	0
T6	110353	0	0	0
T30	1303	3	0	0
T31	2320	0	0	0
T40	822	0	0	0
T41	1920	0	0	0
T42	818	0	0	0
T44	0	3	0	0
T50	1246	0	0	0
T51	0	4	0	0
T52	1623	0	0	0
T60	0	4	0	0
T76	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263720705	154	0	0
T4	25242	0	0	0
T5	12133	0	0	0
T6	110353	0	0	0
T30	1303	3	0	0
T31	2320	0	0	0
T40	822	0	0	0
T41	1920	0	0	0
T42	818	0	0	0
T44	0	3	0	0
T50	1246	0	0	0
T51	0	4	0	0
T52	1623	0	0	0
T60	0	4	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	3	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	128989085	8267	0	0
CgEnOn_A	128989085	6046	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	8267	0	0
T7	578	1	0	0
T8	576	1	0	0
T9	1694	1	0	0
T25	577	1	0	0
T26	566	1	0	0
T27	819	1	0	0
T28	345	1	0	0
T29	4290	3	0	0
T30	674	2	0	0
T31	1154	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128989085	6046	0	0
T1	0	16	0	0
T2	0	53	0	0
T3	0	63	0	0
T4	7086	0	0	0
T5	2798	0	0	0
T6	37888	0	0	0
T12	0	7	0	0
T20	0	1	0	0
T21	0	6	0	0
T29	4290	1	0	0
T30	674	1	0	0
T31	1154	0	0	0
T40	428	0	0	0
T41	937	1	0	0
T44	0	1	0	0
T50	590	0	0	0
T52	906	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	257979464	8326	0	0
CgEnOn_A	257979464	6105	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979464	8326	0	0
T7	1156	1	0	0
T8	1152	1	0	0
T9	3389	1	0	0
T25	1154	1	0	0
T26	1133	1	0	0
T27	1645	1	0	0
T28	691	1	0	0
T29	8580	3	0	0
T30	1348	2	0	0
T31	2309	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257979464	6105	0	0
T1	0	14	0	0
T2	0	53	0	0
T3	0	60	0	0
T4	14179	0	0	0
T5	5593	0	0	0
T6	75776	0	0	0
T12	0	7	0	0
T20	0	1	0	0
T21	0	7	0	0
T29	8580	1	0	0
T30	1348	1	0	0
T31	2309	0	0	0
T40	856	0	0	0
T41	1874	1	0	0
T44	0	1	0	0
T50	1179	0	0	0
T52	1813	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	517264723	8307	0	0
CgEnOn_A	517264723	6076	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517264723	8307	0	0
T7	2236	1	0	0
T8	2438	1	0	0
T9	6493	1	0	0
T25	2239	1	0	0
T26	2162	1	0	0
T27	2862	1	0	0
T28	1455	1	0	0
T29	17320	3	0	0
T30	2816	2	0	0
T31	4642	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517264723	6076	0	0
T1	0	15	0	0
T2	0	56	0	0
T3	0	65	0	0
T4	50483	0	0	0
T5	24265	0	0	0
T6	151576	0	0	0
T12	0	7	0	0
T20	0	1	0	0
T21	0	6	0	0
T29	17320	1	0	0
T30	2816	1	0	0
T31	4642	0	0	0
T40	1643	0	0	0
T41	3840	1	0	0
T44	0	1	0	0
T50	2493	0	0	0
T52	3246	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T44,T51
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	263720705	8311	0	0
CgEnOn_A	263720705	6080	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263720705	8311	0	0
T7	1118	1	0	0
T8	1219	1	0	0
T9	3247	1	0	0
T25	1119	1	0	0
T26	1081	1	0	0
T27	1431	1	0	0
T28	728	1	0	0
T29	8660	3	0	0
T30	1303	4	0	0
T31	2320	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	263720705	6080	0	0
T1	0	16	0	0
T2	0	52	0	0
T3	0	66	0	0
T4	25242	0	0	0
T5	12133	0	0	0
T6	110353	0	0	0
T12	0	7	0	0
T20	0	1	0	0
T21	0	7	0	0
T29	8660	1	0	0
T30	1303	3	0	0
T31	2320	0	0	0
T40	822	0	0	0
T41	1920	1	0	0
T44	0	3	0	0
T50	1246	0	0	0
T52	1623	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Covered	T8,T29,T50
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	4154	0	0
CgEnOn_A	549845917	4153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4154	0	0
T1	0	12	0	0
T8	2539	9	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	5	0	0
T50	0	5	0	0
T52	3381	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4153	0	0
T1	0	12	0	0
T8	2539	9	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	5	0	0
T50	0	5	0	0
T52	3381	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Covered	T8,T29,T50
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	4272	0	0
CgEnOn_A	549845917	4271	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4272	0	0
T1	0	11	0	0
T8	2539	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	3	0	0
T50	0	5	0	0
T52	3381	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4271	0	0
T1	0	11	0	0
T8	2539	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	3	0	0
T50	0	5	0	0
T52	3381	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Covered	T8,T29,T50
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	4163	0	0
CgEnOn_A	549845917	4162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4163	0	0
T1	0	7	0	0
T8	2539	7	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T46	0	6	0	0
T50	0	5	0	0
T52	3381	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4162	0	0
T1	0	7	0	0
T8	2539	7	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T46	0	6	0	0
T50	0	5	0	0
T52	3381	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T4
1	0	Covered	T8,T29,T50
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	549845917	4170	0	0
CgEnOn_A	549845917	4169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4170	0	0
T1	0	8	0	0
T8	2539	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T44	0	1	0	0
T46	0	5	0	0
T50	0	4	0	0
T52	3381	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	549845917	4169	0	0
T1	0	8	0	0
T8	2539	8	0	0
T9	6764	0	0	0
T20	0	1	0	0
T25	2331	0	0	0
T26	2252	0	0	0
T27	2981	0	0	0
T28	1516	0	0	0
T29	18042	1	0	0
T30	2721	3	0	0
T31	4835	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T44	0	1	0	0
T46	0	5	0	0
T50	0	4	0	0
T52	3381	0	0	0